Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate

Masaki Kanemoto, Masaaki Aoki, Akihiro Mochizuki, Yoshio Murakami, Mutsuharu Tsunoda, Goro Yoshinari, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.

Original languageEnglish
Title of host publication2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-3
Number of pages3
Volume2018-January
ISBN (Electronic)9781538612385
DOIs
Publication statusPublished - 2018 Jan 20
Event2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017 - Haining, Zhejiang, China
Duration: 2017 Dec 142017 Dec 16

Other

Other2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
CountryChina
CityHaining, Zhejiang
Period17/12/1417/12/16

Fingerprint

thermal stresses
Thermal stress
chips
solders
Soldering alloys
attachment
sintering
Sintering
thermal cycling tests
Thermal cycling
modulus of elasticity
Physics
Elastic moduli
physics
profiles

Keywords

  • Ag sintering chip-attachment
  • multi-physics solver
  • SiC/Si power devices
  • thermal cycling test
  • thermal stress

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

Cite this

Kanemoto, M., Aoki, M., Mochizuki, A., Murakami, Y., Tsunoda, M., Yoshinari, G., & Nakano, N. (2018). Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. In 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017 (Vol. 2018-January, pp. 1-3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDAPS.2017.8276946

Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. / Kanemoto, Masaki; Aoki, Masaaki; Mochizuki, Akihiro; Murakami, Yoshio; Tsunoda, Mutsuharu; Yoshinari, Goro; Nakano, Nobuhiko.

2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-3.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kanemoto, M, Aoki, M, Mochizuki, A, Murakami, Y, Tsunoda, M, Yoshinari, G & Nakano, N 2018, Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. in 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017, Haining, Zhejiang, China, 17/12/14. https://doi.org/10.1109/EDAPS.2017.8276946
Kanemoto M, Aoki M, Mochizuki A, Murakami Y, Tsunoda M, Yoshinari G et al. Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. In 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-3 https://doi.org/10.1109/EDAPS.2017.8276946
Kanemoto, Masaki ; Aoki, Masaaki ; Mochizuki, Akihiro ; Murakami, Yoshio ; Tsunoda, Mutsuharu ; Yoshinari, Goro ; Nakano, Nobuhiko. / Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-3
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