Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate

Masaki Kanemoto; Masaaki Aoki; Akihiro Mochizuki; Yoshio Murakami; Mutsuharu Tsunoda; Goro Yoshinari; Nobuhiko Nakano

doi:10.1109/EDAPS.2017.8276946

Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate

Masaki Kanemoto, Masaaki Aoki, Akihiro Mochizuki, Yoshio Murakami, Mutsuharu Tsunoda, Goro Yoshinari, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.

Original language	English
Title of host publication	2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
Volume	2018-January
ISBN (Electronic)	9781538612385
DOIs	https://doi.org/10.1109/EDAPS.2017.8276946
Publication status	Published - 2018 Jan 20
Event	2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017 - Haining, Zhejiang, China Duration: 2017 Dec 14 → 2017 Dec 16

Other

Other	2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017
Country/Territory	China
City	Haining, Zhejiang
Period	17/12/14 → 17/12/16

Keywords

Ag sintering chip-attachment
multi-physics solver
SiC/Si power devices
thermal cycling test
thermal stress

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Instrumentation

Access to Document

10.1109/EDAPS.2017.8276946

Cite this

Kanemoto, M., Aoki, M., Mochizuki, A., Murakami, Y., Tsunoda, M., Yoshinari, G., & Nakano, N. (2018). Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. In 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017 (Vol. 2018-January, pp. 1-3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDAPS.2017.8276946

Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. / Kanemoto, Masaki; Aoki, Masaaki; Mochizuki, Akihiro et al.

2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-3.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kanemoto, M, Aoki, M, Mochizuki, A, Murakami, Y, Tsunoda, M, Yoshinari, G & Nakano, N 2018, Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. in 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017, Haining, Zhejiang, China, 17/12/14. https://doi.org/10.1109/EDAPS.2017.8276946

Kanemoto M, Aoki M, Mochizuki A, Murakami Y, Tsunoda M, Yoshinari G et al. Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate. In 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-3 doi: 10.1109/EDAPS.2017.8276946

@inproceedings{32f5d750c9a94d7aa6d6b22ac397fdd4,

title = "Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate",

abstract = "This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.",

keywords = "Ag sintering chip-attachment, multi-physics solver, SiC/Si power devices, thermal cycling test, thermal stress",

author = "Masaki Kanemoto and Masaaki Aoki and Akihiro Mochizuki and Yoshio Murakami and Mutsuharu Tsunoda and Goro Yoshinari and Nobuhiko Nakano",

year = "2018",

month = jan,

day = "20",

doi = "10.1109/EDAPS.2017.8276946",

language = "English",

volume = "2018-January",

pages = "1--3",

booktitle = "2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017 ; Conference date: 14-12-2017 Through 16-12-2017",

}

TY - GEN

T1 - Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate

AU - Kanemoto, Masaki

AU - Aoki, Masaaki

AU - Mochizuki, Akihiro

AU - Murakami, Yoshio

AU - Tsunoda, Mutsuharu

AU - Yoshinari, Goro

AU - Nakano, Nobuhiko

PY - 2018/1/20

Y1 - 2018/1/20

N2 - This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.

AB - This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.

KW - Ag sintering chip-attachment

KW - multi-physics solver

KW - SiC/Si power devices

KW - thermal cycling test

KW - thermal stress

UR - http://www.scopus.com/inward/record.url?scp=85050469318&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85050469318&partnerID=8YFLogxK

U2 - 10.1109/EDAPS.2017.8276946

DO - 10.1109/EDAPS.2017.8276946

M3 - Conference contribution

AN - SCOPUS:85050469318

VL - 2018-January

SP - 1

EP - 3

BT - 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017

Y2 - 14 December 2017 through 16 December 2017

ER -

Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate

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Keywords

ASJC Scopus subject areas

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