### Abstract

Quantum algorithms can be written down in several forms, one of the most common is the quantum circuit representation using discrete gates. The challenge in assessing the computational cost then becomes counting those gates, with realistic costs assigned to each gate. Moreover, interacting pairs of qubits inside most quantum computers will require moving qubits. In many architectures, this will involve cellular automaton-like swapping of qubits. In general, the depth will be described in number of quantum error correction (QEC) cycles, while the total cost will be space-time ''volume'' consisting of the number of qubits involved over that set of QEC cycles. This implies that accurate estimates can be made only in the context of a particular architecture and error correction mechanism.

Original language | English |
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Title of host publication | Proceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012 |

Pages | 50-54 |

Number of pages | 5 |

DOIs | |

Publication status | Published - 2012 Dec 1 |

Event | 2012 IEEE 21st Asian Test Symposium, ATS 2012 - Niigatta, Japan Duration: 2012 Nov 19 → 2012 Nov 22 |

### Publication series

Name | Proceedings of the Asian Test Symposium |
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ISSN (Print) | 1081-7735 |

### Other

Other | 2012 IEEE 21st Asian Test Symposium, ATS 2012 |
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Country | Japan |

City | Niigatta |

Period | 12/11/19 → 12/11/22 |

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### Keywords

- Compilation
- Optimization
- Quantum computation

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*Proceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012*(pp. 50-54). [6394171] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2012.67