Abstract
Because of the increase in cost for chip fabrication, design-ing a chip family in accordance with the application is be-coming an expensive choice. Wireless 3D IC design offers flexibility to connect known-good-dies selected after chip fabrication. It can stack an arbitrary number of chips at low cost. In this paper, dynamic time division multiple access (D-TDMA) is used for vertical broadcast buses for high communication efficiency of interchip network. However, to implement simple D-TDMA based 3D IC, large area and energy overheads are needed for arbitration since another inductor is needed for sending just several bits as arbitra-tion signal in addition to an inductor for the data transfer. We resolve this problem to employ a carrier sense multiple access with collision detection (CSMA/CD) for arbitration of D-TDMA vertical broadcast buses. Evaluation results show that the proposed bus architecture reduces the num-ber of inductors by 73.6% compared to a simple counter-part which employs D-TDMA based 3D buses. The results also show that an application execution time increases only by 0.3% at most.
Original language | English |
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Title of host publication | Proceedings of the 13th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2016 |
Publisher | Acta Press |
Pages | 242-249 |
Number of pages | 8 |
ISBN (Electronic) | 9780889869790 |
DOIs | |
Publication status | Published - 2016 |
Event | 13th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2016 - Innsbruck, Austria Duration: 2016 Feb 15 → 2016 Feb 16 |
Other
Other | 13th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2016 |
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Country/Territory | Austria |
City | Innsbruck |
Period | 16/2/15 → 16/2/16 |
Keywords
- Bus
- Chip Multi-Processor
- Network-on-Chip
- Wireless 3D IC
ASJC Scopus subject areas
- Computer Networks and Communications
- Software