Daisy chain for power reduction in inductive-coupling CMOS link

Mari Inoue; Noriyuki Miura; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda

Daisy chain for power reduction in inductive-coupling CMOS link

Mari Inoue, Noriyuki Miura, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

This paper discusses a daisy chain of current-drive transmitters in inductive-coupling CMOS links. Current is reused by multiple transmitters. 8 transceivers are arranged with a pitch of 20μm in 0.18μm CMOS. Transmit power is saved by 35% without sacrificing data rate (1Gb/s/ch) and BER (<10^-12) by having 4 transmitters daisy chained.

Original language	English
Title of host publication	2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	65-66
Number of pages	2
Publication status	Published - 2006
Event	2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: 2006 Jun 15 → 2006 Jun 17

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2006 Symposium on VLSI Circuits, VLSIC
Country/Territory	United States
City	Honolulu, HI
Period	06/6/15 → 06/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Inoue, M, Miura, N, Niitsu, K, Nakagawa, Y, Tago, M, Fukaishi, M, Sakurai, T & Kuroda, T 2006, Daisy chain for power reduction in inductive-coupling CMOS link. in 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 1705314, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 65-66, 2006 Symposium on VLSI Circuits, VLSIC, Honolulu, HI, United States, 06/6/15.

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author = "Mari Inoue and Noriyuki Miura and Kiichi Niitsu and Yoshihiro Nakagawa and Masamoto Tago and Muneo Fukaishi and Takayasu Sakurai and Tadahiro Kuroda",

year = "2006",

language = "English",

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series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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AU - Inoue, Mari

AU - Miura, Noriyuki

AU - Niitsu, Kiichi

AU - Nakagawa, Yoshihiro

AU - Tago, Masamoto

AU - Fukaishi, Muneo

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2006

Y1 - 2006

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AB - This paper discusses a daisy chain of current-drive transmitters in inductive-coupling CMOS links. Current is reused by multiple transmitters. 8 transceivers are arranged with a pitch of 20μm in 0.18μm CMOS. Transmit power is saved by 35% without sacrificing data rate (1Gb/s/ch) and BER (<10-12) by having 4 transmitters daisy chained.

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M3 - Conference contribution

AN - SCOPUS:34548829219

SN - 1424400066

SN - 9781424400065

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 65

EP - 66

BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers

T2 - 2006 Symposium on VLSI Circuits, VLSIC

Y2 - 15 June 2006 through 17 June 2006

ER -

Daisy chain for power reduction in inductive-coupling CMOS link

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ASJC Scopus subject areas

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