Daisy chain for power reduction in inductive-coupling CMOS link

Mari Inoue, Noriyuki Miura, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

This paper discusses a daisy chain of current-drive transmitters in inductive-coupling CMOS links. Current is reused by multiple transmitters. 8 transceivers are arranged with a pitch of 20μm in 0.18μm CMOS. Transmit power is saved by 35% without sacrificing data rate (1Gb/s/ch) and BER (<10-12) by having 4 transmitters daisy chained.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages65-66
Number of pages2
Publication statusPublished - 2006
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period06/6/1506/6/17

Fingerprint

Transmitters
Transceivers
Telecommunication links

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Inoue, M., Miura, N., Niitsu, K., Nakagawa, Y., Tago, M., Fukaishi, M., ... Kuroda, T. (2006). Daisy chain for power reduction in inductive-coupling CMOS link. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 65-66). [1705314]

Daisy chain for power reduction in inductive-coupling CMOS link. / Inoue, Mari; Miura, Noriyuki; Niitsu, Kiichi; Nakagawa, Yoshihiro; Tago, Masamoto; Fukaishi, Muneo; Sakurai, Takayasu; Kuroda, Tadahiro.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 65-66 1705314.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inoue, M, Miura, N, Niitsu, K, Nakagawa, Y, Tago, M, Fukaishi, M, Sakurai, T & Kuroda, T 2006, Daisy chain for power reduction in inductive-coupling CMOS link. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 1705314, pp. 65-66, 2006 Symposium on VLSI Circuits, VLSIC, Honolulu, HI, United States, 06/6/15.
Inoue M, Miura N, Niitsu K, Nakagawa Y, Tago M, Fukaishi M et al. Daisy chain for power reduction in inductive-coupling CMOS link. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 65-66. 1705314
Inoue, Mari ; Miura, Noriyuki ; Niitsu, Kiichi ; Nakagawa, Yoshihiro ; Tago, Masamoto ; Fukaishi, Muneo ; Sakurai, Takayasu ; Kuroda, Tadahiro. / Daisy chain for power reduction in inductive-coupling CMOS link. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. pp. 65-66
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