Data movement optimization for software-controlled on-chip memory

Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In order to overcome performance degradation caused by performance disparity between processor and main memory, there have been proposed several new VLSI architectures which have software controlled on-chip memory in addition to the conventional cache. However, users must specify data allocation/replacement on software controlled on-chip memory and data transfer between the on-chip and off-chip memories to achieve higher performance by utilizing on-chip memory. Because such properties are automatically controlled by hardware in conventional caches, a cost of optimization for a program becomes a matter that should be considered. In this paper, we propose an data movement optimization technique for software-controlled on-chip memory. We evaluated the proposed method using two applications. The results reveal that the proposed technique can drastically reduce memory stall cycles and achieve high performance.

Original languageEnglish
Title of host publicationProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004
Pages120-127
Number of pages8
DOIs
Publication statusPublished - 2004
Externally publishedYes
EventProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004 - Madrid, Spain
Duration: 2004 Feb 152004 Feb 15

Publication series

NameProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004

Conference

ConferenceProceedings - Eighth Workshop on Interaction between Compilers and Computer Architectures, INTERACT-8 2004
Country/TerritorySpain
CityMadrid
Period04/2/1504/2/15

ASJC Scopus subject areas

  • Engineering(all)

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