Descending layers routing

A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies

M. Koibuchi, A. Jouraku, K. Watanabe, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

System area networks (SANs), which usually accept irregular topologies, have been used to connect nodes in PC/WS clusters or high-performance storage systems. Since wormhole or virtual cut-through transfer is used for low latency communication, deadlock-free routings are essential in SANs. We propose a novel deadlock-free deterministic routing called descending layers (DL) routing for SANs. In order to reduce both nonminimal paths and traffic congestion, the network is divided into layers of subnetworks with the same topology using virtual channels, and a large number of paths across multiple subnetworks are established. The DL routing is implemented on a real PC cluster called RHiNET-2, and execution results show that its throughput is improved up to 33% compared with that of up∗/down∗ routing. Its execution time of a barrier synchronization is also improved 29% compared with that of up∗/down∗ routing. Simulation results of various sizes and topologies also show that the DL routing achieves up to 266% improvement on throughput compared with up∗/down∗ routing.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages527-536
Number of pages10
Volume2003-January
ISBN (Print)0769520170
DOIs
Publication statusPublished - 2003
Event2003 International Conference on Parallel Processing, ICPP 2003 - Kaohsiung, Taiwan, Province of China
Duration: 2003 Oct 62003 Oct 9

Other

Other2003 International Conference on Parallel Processing, ICPP 2003
CountryTaiwan, Province of China
CityKaohsiung
Period03/10/603/10/9

Fingerprint

Virtual Channel
Deadlock
Irregular
Routing
Topology
HPSS
Throughput
Traffic congestion
Synchronization
Communication
PC Cluster
Path
Wormhole
Traffic Congestion
Storage System
Execution Time
Latency
High Performance

Keywords

  • Fabrics
  • Intelligent networks
  • Multiprocessor interconnection networks
  • Network topology
  • Packet switching
  • Parallel processing
  • Routing
  • System recovery
  • Telecommunication traffic
  • Throughput

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Koibuchi, M., Jouraku, A., Watanabe, K., & Amano, H. (2003). Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies. In Proceedings of the International Conference on Parallel Processing (Vol. 2003-January, pp. 527-536). [1240620] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.2003.1240620

Descending layers routing : A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies. / Koibuchi, M.; Jouraku, A.; Watanabe, K.; Amano, Hideharu.

Proceedings of the International Conference on Parallel Processing. Vol. 2003-January Institute of Electrical and Electronics Engineers Inc., 2003. p. 527-536 1240620.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Koibuchi, M, Jouraku, A, Watanabe, K & Amano, H 2003, Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies. in Proceedings of the International Conference on Parallel Processing. vol. 2003-January, 1240620, Institute of Electrical and Electronics Engineers Inc., pp. 527-536, 2003 International Conference on Parallel Processing, ICPP 2003, Kaohsiung, Taiwan, Province of China, 03/10/6. https://doi.org/10.1109/ICPP.2003.1240620
Koibuchi M, Jouraku A, Watanabe K, Amano H. Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies. In Proceedings of the International Conference on Parallel Processing. Vol. 2003-January. Institute of Electrical and Electronics Engineers Inc. 2003. p. 527-536. 1240620 https://doi.org/10.1109/ICPP.2003.1240620
Koibuchi, M. ; Jouraku, A. ; Watanabe, K. ; Amano, Hideharu. / Descending layers routing : A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies. Proceedings of the International Conference on Parallel Processing. Vol. 2003-January Institute of Electrical and Electronics Engineers Inc., 2003. pp. 527-536
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