Design and analysis for ThruChip design for manufacturing (DFM)

Li Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    A 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission

    Original languageEnglish
    Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages46-47
    Number of pages2
    ISBN (Electronic)9781479977925
    DOIs
    Publication statusPublished - 2015 Mar 11
    Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
    Duration: 2015 Jan 192015 Jan 22

    Publication series

    Name20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

    Other

    Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
    CountryJapan
    CityChiba
    Period15/1/1915/1/22

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering
    • Control and Systems Engineering
    • Modelling and Simulation

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