Design and implementation of a handshake join architecture on FPGA

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

Original languageEnglish
Pages (from-to)2919-2927
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE95-D
Issue number12
DOIs
Publication statusPublished - 2012 Jan 1
Externally publishedYes

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Clocks
Tuning

Keywords

  • Accelerator
  • Data stream processing
  • FPGA
  • Handshake join
  • Window join operator

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence
  • Electrical and Electronic Engineering

Cite this

Design and implementation of a handshake join architecture on FPGA. / Oge, Yasin; Miyoshi, Takefumi; Kawashima, Hideyuki; Yoshinaga, Tsutomu.

In: IEICE Transactions on Information and Systems, Vol. E95-D, No. 12, 01.01.2012, p. 2919-2927.

Research output: Contribution to journalArticle

Oge, Yasin ; Miyoshi, Takefumi ; Kawashima, Hideyuki ; Yoshinaga, Tsutomu. / Design and implementation of a handshake join architecture on FPGA. In: IEICE Transactions on Information and Systems. 2012 ; Vol. E95-D, No. 12. pp. 2919-2927.
@article{920921a4cd734d4bb1f57479bbaa34da,
title = "Design and implementation of a handshake join architecture on FPGA",
abstract = "A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.",
keywords = "Accelerator, Data stream processing, FPGA, Handshake join, Window join operator",
author = "Yasin Oge and Takefumi Miyoshi and Hideyuki Kawashima and Tsutomu Yoshinaga",
year = "2012",
month = "1",
day = "1",
doi = "10.1587/transinf.E95.D.2919",
language = "English",
volume = "E95-D",
pages = "2919--2927",
journal = "IEICE Transactions on Information and Systems",
issn = "0916-8532",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Design and implementation of a handshake join architecture on FPGA

AU - Oge, Yasin

AU - Miyoshi, Takefumi

AU - Kawashima, Hideyuki

AU - Yoshinaga, Tsutomu

PY - 2012/1/1

Y1 - 2012/1/1

N2 - A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

AB - A novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

KW - Accelerator

KW - Data stream processing

KW - FPGA

KW - Handshake join

KW - Window join operator

UR - http://www.scopus.com/inward/record.url?scp=84870708424&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84870708424&partnerID=8YFLogxK

U2 - 10.1587/transinf.E95.D.2919

DO - 10.1587/transinf.E95.D.2919

M3 - Article

AN - SCOPUS:84870708424

VL - E95-D

SP - 2919

EP - 2927

JO - IEICE Transactions on Information and Systems

JF - IEICE Transactions on Information and Systems

SN - 0916-8532

IS - 12

ER -