Design and implementation of a merging network architecture for handshake join operator on fpga

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

A novel merging network architecture is proposed for a handshake join operator in order to achieve much higher data throughput than ever before. Handshake join is a highly parallelized algorithm for window-based stream joins. Result collection performed by a merging network is a significant design issue for the handshake join operator because the merging network becomes an overwhelming bottleneck for scalable performance. To address the issue, an adaptive merging network is proposed for hardware implementation of the algorithm. The proposed architecture is implemented on an FPGA and it is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results demonstrate up to 16.3 times higher throughput than nested loops-style join implementation without dropping any tuples. To the best of our knowledge, this is the best performance for handshake join operator implemented on an FPGA.

Original languageEnglish
Pages84-91
Number of pages8
DOIs
Publication statusPublished - 2012 Dec 1
Externally publishedYes
Event2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012 - Aizu-Wakamatsu, Fukushima, Japan
Duration: 2012 Sep 202012 Sep 22

Other

Other2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012
CountryJapan
CityAizu-Wakamatsu, Fukushima
Period12/9/2012/9/22

Fingerprint

Network architecture
Merging
Field programmable gate arrays (FPGA)
Throughput
Hardware
Clocks

Keywords

  • Data stream processing
  • FPGA
  • Handshake join
  • Merging network
  • Window join operator

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Oge, Y., Miyoshi, T., Kawashima, H., & Yoshinaga, T. (2012). Design and implementation of a merging network architecture for handshake join operator on fpga. 84-91. Paper presented at 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012, Aizu-Wakamatsu, Fukushima, Japan. https://doi.org/10.1109/MCSoC.2012.21

Design and implementation of a merging network architecture for handshake join operator on fpga. / Oge, Yasin; Miyoshi, Takefumi; Kawashima, Hideyuki; Yoshinaga, Tsutomu.

2012. 84-91 Paper presented at 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012, Aizu-Wakamatsu, Fukushima, Japan.

Research output: Contribution to conferencePaper

Oge, Y, Miyoshi, T, Kawashima, H & Yoshinaga, T 2012, 'Design and implementation of a merging network architecture for handshake join operator on fpga', Paper presented at 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012, Aizu-Wakamatsu, Fukushima, Japan, 12/9/20 - 12/9/22 pp. 84-91. https://doi.org/10.1109/MCSoC.2012.21
Oge Y, Miyoshi T, Kawashima H, Yoshinaga T. Design and implementation of a merging network architecture for handshake join operator on fpga. 2012. Paper presented at 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012, Aizu-Wakamatsu, Fukushima, Japan. https://doi.org/10.1109/MCSoC.2012.21
Oge, Yasin ; Miyoshi, Takefumi ; Kawashima, Hideyuki ; Yoshinaga, Tsutomu. / Design and implementation of a merging network architecture for handshake join operator on fpga. Paper presented at 2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012, Aizu-Wakamatsu, Fukushima, Japan.8 p.
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