Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Viterbi decoder implemented with hard-wired logic often requires extra cost and consuming power by using individual logic for various constraint length and decode precisions. Although the redundant hardware which is not used in the given condition can be omitted by replacing the hard-wired logic on FPGA, the time for loading configuration data often takes milliseconds and causes too long system stall. In this paper, we implemented the Viterbi algorithms whose constraint length are from 3 to 5 on coarse grained dynamically reconfigurable processor DAPDNA-II and replaced them according to the requirement. A certain thresh-old of BER is set for a fixed SNR and the Viterbi decoder with multiple constraint lengths is simulated. In the result of evaluation, when at least 4.50 Mbps throughput is ensured even with frequent reconfiguration was performed, the power consumption is reduced by 30% - 80% compared with the case when a constraint length of the best performance is utilized.

Original languageEnglish
Title of host publicationProceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008
Pages247-252
Number of pages6
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008 - Cancun, Mexico
Duration: 2008 Dec 32008 Dec 5

Other

Other2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008
CountryMexico
CityCancun
Period08/12/308/12/5

Fingerprint

Viterbi algorithm
Field programmable gate arrays (FPGA)
Electric power utilization
Throughput
Hardware
Costs

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Kishimoto, Y., Haruyama, S., & Amano, H. (2008). Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor. In Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008 (pp. 247-252). [4731802] https://doi.org/10.1109/ReConFig.2008.39

Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor. / Kishimoto, Yuken; Haruyama, Shinichiro; Amano, Hideharu.

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. 2008. p. 247-252 4731802.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kishimoto, Y, Haruyama, S & Amano, H 2008, Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor. in Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008., 4731802, pp. 247-252, 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008, Cancun, Mexico, 08/12/3. https://doi.org/10.1109/ReConFig.2008.39
Kishimoto Y, Haruyama S, Amano H. Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor. In Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. 2008. p. 247-252. 4731802 https://doi.org/10.1109/ReConFig.2008.39
Kishimoto, Yuken ; Haruyama, Shinichiro ; Amano, Hideharu. / Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor. Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. 2008. pp. 247-252
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