Design and implementation of hardware cache mechanism and NIC for column-oriented databases

Akihiko Hamada, Hiroki Matsutani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently some researches to utilize big data efficiently have been made vigorously. To store and process big data, structured storages (NOSQLs) that have high degree of horizontal scalability have attracted a lot of attention. Key-value stores and column-oriented stores are known as famous examples of structured storages. Especially, column-oriented stores can store variable numbers of columns for each row while maintaining high scalability. Moreover, range queries (scan operations) are supported in column-oriented stores. This paper proposes hardware cache mechanism using FPGA NIC to accelerate column-oriented databases. In this paper, it is assumed that column-oriented stores running on database servers are accessed by clients via a network. This paper aims to improve performance and power efficiency of column-oriented stores by introducing an FPGA-based 10GbE network interface (NIC) and a hardware cache mechanism (HBC) implemented on the NIC. HBC stores query results (sorted rows) as a key-value form in the DRAM implemented on the FPGA NIC, and the requested data can be returned to clients immediately if the query result has been cached. Existing work that aims to accelerate structured storages by hardware have focused only on key-value stores while column-oriented stores that support range queries (scan operations) have not been addressed. HBC deploys methods that address data mappings and range queries of caches using specific data structures that can be represented in binary-Tree forms and this paper shows HBC can accelerate range queries by hardware. In experiments of this paper, HBase is running on an application layer, while HBC is implemented on an FPGA-based NIC. This paper shows that improvement of power efficiency and significant performance improvement can be achieved by the proposed HBC and also pros and cons of the proposed HBC are discussed.

Original languageEnglish
Title of host publication2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
EditorsPeter Athanas, Rene Cumplido, Claudia Feregrino, Ron Sass
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509037070
DOIs
Publication statusPublished - 2016 Jan 1
Event2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 - Cancun, Mexico
Duration: 2016 Nov 302016 Dec 2

Publication series

Name2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016

Other

Other2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
CountryMexico
CityCancun
Period16/11/3016/12/2

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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    Hamada, A., & Matsutani, H. (2016). Design and implementation of hardware cache mechanism and NIC for column-oriented databases. In P. Athanas, R. Cumplido, C. Feregrino, & R. Sass (Eds.), 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 [7857164] (2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ReConFig.2016.7857164