Design and implementation of on-chip adaptive router with predictor for regional congestion

Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Many-core processor is one of attractive solutions to Cyber-Physical Systems (CPS) that demands high computational power since it can enclose many computational elements into a single physical chip. Network-on-Chip (NoC) that connects the processing cores is the key in terms of the cost, performance, and power in such systems. Although NoCs typically employ simple deterministic routing algorithms in order to reduce the complexity of on-chip routers, such deterministic algorithms do not avoid traffic congestion and thus the network throughput is degraded when the traffic pattern has localities. On the other hand, complex algorithms require large hardware cost and will be a problem for CPS whose hardware cost is limited. In this paper, we propose an adaptive on-chip router with Predictor for Regional Congestion (PRC) in order to improve the network throughput with modest hardware overhead. The proposed PRC routers exchange their past and predicted future congestion information with each other. Then, each router synthesizes its regional congestion information based on the local and received information in order to route packets without congestion. The simulation results show that the proposed routers improve the average throughput by 17.2% compared to a congestion-aware router that employes local information only. The RTL design of the proposed router shows that the area overhead is only 2.6% and additional wiring requirement for each router port is only three.

Original languageEnglish
Title of host publicationProceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
Pages22-27
Number of pages6
Volume2
DOIs
Publication statusPublished - 2011
Event1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama, Japan
Duration: 2011 Aug 282011 Aug 31

Other

Other1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
CountryJapan
CityToyama
Period11/8/2811/8/31

Fingerprint

Routers
Throughput
Computer hardware
Costs
Traffic congestion
Electric wiring
Routing algorithms
Hardware
Processing

Keywords

  • Adaptive routing
  • Modest hardware overhead
  • Network-on-Chip
  • Prediction
  • Transmit congestion information

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Networks and Communications

Cite this

Taniguchi, M., Matsutani, H., & Yamasaki, N. (2011). Design and implementation of on-chip adaptive router with predictor for regional congestion. In Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011 (Vol. 2, pp. 22-27). [602904] https://doi.org/10.1109/RTCSA.2011.61

Design and implementation of on-chip adaptive router with predictor for regional congestion. / Taniguchi, Masakazu; Matsutani, Hiroki; Yamasaki, Nobuyuki.

Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2 2011. p. 22-27 602904.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Taniguchi, M, Matsutani, H & Yamasaki, N 2011, Design and implementation of on-chip adaptive router with predictor for regional congestion. in Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. vol. 2, 602904, pp. 22-27, 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011, Toyama, Japan, 11/8/28. https://doi.org/10.1109/RTCSA.2011.61
Taniguchi M, Matsutani H, Yamasaki N. Design and implementation of on-chip adaptive router with predictor for regional congestion. In Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2. 2011. p. 22-27. 602904 https://doi.org/10.1109/RTCSA.2011.61
Taniguchi, Masakazu ; Matsutani, Hiroki ; Yamasaki, Nobuyuki. / Design and implementation of on-chip adaptive router with predictor for regional congestion. Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2 2011. pp. 22-27
@inproceedings{3120d7c916784888ad9030a39cba02b0,
title = "Design and implementation of on-chip adaptive router with predictor for regional congestion",
abstract = "Many-core processor is one of attractive solutions to Cyber-Physical Systems (CPS) that demands high computational power since it can enclose many computational elements into a single physical chip. Network-on-Chip (NoC) that connects the processing cores is the key in terms of the cost, performance, and power in such systems. Although NoCs typically employ simple deterministic routing algorithms in order to reduce the complexity of on-chip routers, such deterministic algorithms do not avoid traffic congestion and thus the network throughput is degraded when the traffic pattern has localities. On the other hand, complex algorithms require large hardware cost and will be a problem for CPS whose hardware cost is limited. In this paper, we propose an adaptive on-chip router with Predictor for Regional Congestion (PRC) in order to improve the network throughput with modest hardware overhead. The proposed PRC routers exchange their past and predicted future congestion information with each other. Then, each router synthesizes its regional congestion information based on the local and received information in order to route packets without congestion. The simulation results show that the proposed routers improve the average throughput by 17.2{\%} compared to a congestion-aware router that employes local information only. The RTL design of the proposed router shows that the area overhead is only 2.6{\%} and additional wiring requirement for each router port is only three.",
keywords = "Adaptive routing, Modest hardware overhead, Network-on-Chip, Prediction, Transmit congestion information",
author = "Masakazu Taniguchi and Hiroki Matsutani and Nobuyuki Yamasaki",
year = "2011",
doi = "10.1109/RTCSA.2011.61",
language = "English",
isbn = "9780769545028",
volume = "2",
pages = "22--27",
booktitle = "Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011",

}

TY - GEN

T1 - Design and implementation of on-chip adaptive router with predictor for regional congestion

AU - Taniguchi, Masakazu

AU - Matsutani, Hiroki

AU - Yamasaki, Nobuyuki

PY - 2011

Y1 - 2011

N2 - Many-core processor is one of attractive solutions to Cyber-Physical Systems (CPS) that demands high computational power since it can enclose many computational elements into a single physical chip. Network-on-Chip (NoC) that connects the processing cores is the key in terms of the cost, performance, and power in such systems. Although NoCs typically employ simple deterministic routing algorithms in order to reduce the complexity of on-chip routers, such deterministic algorithms do not avoid traffic congestion and thus the network throughput is degraded when the traffic pattern has localities. On the other hand, complex algorithms require large hardware cost and will be a problem for CPS whose hardware cost is limited. In this paper, we propose an adaptive on-chip router with Predictor for Regional Congestion (PRC) in order to improve the network throughput with modest hardware overhead. The proposed PRC routers exchange their past and predicted future congestion information with each other. Then, each router synthesizes its regional congestion information based on the local and received information in order to route packets without congestion. The simulation results show that the proposed routers improve the average throughput by 17.2% compared to a congestion-aware router that employes local information only. The RTL design of the proposed router shows that the area overhead is only 2.6% and additional wiring requirement for each router port is only three.

AB - Many-core processor is one of attractive solutions to Cyber-Physical Systems (CPS) that demands high computational power since it can enclose many computational elements into a single physical chip. Network-on-Chip (NoC) that connects the processing cores is the key in terms of the cost, performance, and power in such systems. Although NoCs typically employ simple deterministic routing algorithms in order to reduce the complexity of on-chip routers, such deterministic algorithms do not avoid traffic congestion and thus the network throughput is degraded when the traffic pattern has localities. On the other hand, complex algorithms require large hardware cost and will be a problem for CPS whose hardware cost is limited. In this paper, we propose an adaptive on-chip router with Predictor for Regional Congestion (PRC) in order to improve the network throughput with modest hardware overhead. The proposed PRC routers exchange their past and predicted future congestion information with each other. Then, each router synthesizes its regional congestion information based on the local and received information in order to route packets without congestion. The simulation results show that the proposed routers improve the average throughput by 17.2% compared to a congestion-aware router that employes local information only. The RTL design of the proposed router shows that the area overhead is only 2.6% and additional wiring requirement for each router port is only three.

KW - Adaptive routing

KW - Modest hardware overhead

KW - Network-on-Chip

KW - Prediction

KW - Transmit congestion information

UR - http://www.scopus.com/inward/record.url?scp=84855542450&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84855542450&partnerID=8YFLogxK

U2 - 10.1109/RTCSA.2011.61

DO - 10.1109/RTCSA.2011.61

M3 - Conference contribution

SN - 9780769545028

VL - 2

SP - 22

EP - 27

BT - Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011

ER -