Design automation methodology of a critical path monitor for adaptive voltage controls

Ryosuke Kazami, Hayate Okuhara, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The development of recent CMOS technologies such as Fully Depleted Silicon on Insulator (FD-SOI) allows VLSI systems to operate with lower power than the conventional bulk transistors [1, 2]. Thanks to its high degree of noise immunity, low power supply voltages (VDD) can be applied to the FD-SOI devices. Also, since the effect of body biasing is further endorsed in such devices, adaptive voltage control for both power supply voltage and body bias voltages (VBN for nMOS and VBP for pMOS) can be aggressively used.

Original languageEnglish
Title of host publication21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-3
Number of pages3
ISBN (Electronic)9781538661024
DOIs
Publication statusPublished - 2018 Jun 5
Event21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Yokohama, Japan
Duration: 2018 Apr 182018 Apr 20

Other

Other21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018
CountryJapan
CityYokohama
Period18/4/1818/4/20

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kazami, R., Okuhara, H., & Amano, H. (2018). Design automation methodology of a critical path monitor for adaptive voltage controls. In 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings (pp. 1-3). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CoolChips.2018.8373073