Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tanbunheng, Takuro Nakamura, Takashi Nishimura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and an inter-PE connection is fixed, the array size, PE granularity, and connection flexibilities of intra/inter PE are selectable. In this paper, we have generated various types of DRPAs and evaluated semiconductor area and speed by using the AS-PLA/STARC 90-nm CMOS technology. From evaluation results, fundamental trade-offs between architectural parameters and area/delay are analyzed.

Original languageEnglish
Title of host publicationProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages796-799
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: 2007 Aug 272007 Aug 29

Publication series

NameProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2007 International Conference on Field Programmable Logic and Applications, FPL
CountryNetherlands
CityAmsterdam
Period07/8/2707/8/29

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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  • Cite this

    Hasegawa, Y., Tsutsumi, S., Tanbunheng, V., Nakamura, T., Nishimura, T., & Amano, H. (2007). Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays. In Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL (pp. 796-799). [4380771] (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL). https://doi.org/10.1109/FPL.2007.4380771