Design of a low power NoC router using marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Power consumption of Network-on-Chip (NoC) is becoming more important in many core processors. Input buffers utilized in routers consume a significant part of the total power of NoCs. In order to reduce this power consumption, a novel power efficient memory called Marching Memory Through type (MMTH) is introduced. By connecting transparent latches in tandem, MMTH achieves high speed operation with a low power consumption. MMTH, however, requires a certain overhead at read operation, and hence we propose a latency reduction scheme based on the look-ahead routing. The proposed router was designed in Renesas's 40nm process and compared with a standard router using conventional register-based FIFOs in terms of the network performance, application performance, and power consumption. The result of evaluation shows that the proposed router reduces the power consumption by 42.4% on average at 2GHz and the expense of only 0.5-2.0% performance overhead.

Original languageEnglish
Title of host publicationProceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
EditorsDavide Bertozzi, Luca Benini, Sudhakar Yalamanchili, Joerg Henkel
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages111-118
Number of pages8
ISBN (Electronic)9781479953479
DOIs
Publication statusPublished - 2015 Jan 13
Event8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014 - Ferrara, Italy
Duration: 2014 Sep 172014 Sep 19

Publication series

NameProceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014

Other

Other8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014
CountryItaly
CityFerrara
Period14/9/1714/9/19

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanabe, M., Oishi, T., Shimizu, T., & Nakamura, T. (2015). Design of a low power NoC router using marching memory through type. In D. Bertozzi, L. Benini, S. Yalamanchili, & J. Henkel (Eds.), Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014 (pp. 111-118). [7008769] (Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NOCS.2014.7008769