Design of new logic architectures utilizing optimized suspended-gate single-electron transistors

Benjamin Pruvost, Ken Uchida, Hiroshi Mizuta, Shunri Oda

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.

Original languageEnglish
Article number5223702
Pages (from-to)504-512
Number of pages9
JournalIEEE Transactions on Nanotechnology
Volume9
Issue number4
DOIs
Publication statusPublished - 2010 Jul
Externally publishedYes

Fingerprint

Single electron transistors
Nonlinear networks
Pattern matching
SPICE
Analytical models
Capacitors
Networks (circuits)
Electric potential

Keywords

  • 1-D and 3-D modeling
  • cantilever switch
  • movable gate
  • nanoelectromechanical system (NEMS)
  • single-electron transistor (SET)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Design of new logic architectures utilizing optimized suspended-gate single-electron transistors. / Pruvost, Benjamin; Uchida, Ken; Mizuta, Hiroshi; Oda, Shunri.

In: IEEE Transactions on Nanotechnology, Vol. 9, No. 4, 5223702, 07.2010, p. 504-512.

Research output: Contribution to journalArticle

Pruvost, Benjamin ; Uchida, Ken ; Mizuta, Hiroshi ; Oda, Shunri. / Design of new logic architectures utilizing optimized suspended-gate single-electron transistors. In: IEEE Transactions on Nanotechnology. 2010 ; Vol. 9, No. 4. pp. 504-512.
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