Design of phase-controlled class E inverter with asymmetric circuit configuration

Daisuke Kawamoto, Hiroo Sekiya, Hirotaka Koizumi, Iwao Sasase, Shinsaku Mori

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

A design of phase-controlled class E inverter with asymmetric circuit configuration is presented. By using the presented design method, it is possible to derive the design values, which let the inverters achieve zero-voltage switching continuously in the control range, are derived. By carrying out circuit experiments, it is verified that the experimental results agree with numerical predictions quantitatively, and the validity of the presented design procedure is denoted.

Original languageEnglish
Pages (from-to)523-528
Number of pages6
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume51
Issue number10
DOIs
Publication statusPublished - 2004 Oct

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Networks (circuits)
Zero voltage switching
Experiments

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

Cite this

Design of phase-controlled class E inverter with asymmetric circuit configuration. / Kawamoto, Daisuke; Sekiya, Hiroo; Koizumi, Hirotaka; Sasase, Iwao; Mori, Shinsaku.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 51, No. 10, 10.2004, p. 523-528.

Research output: Contribution to journalArticle

Kawamoto, Daisuke ; Sekiya, Hiroo ; Koizumi, Hirotaka ; Sasase, Iwao ; Mori, Shinsaku. / Design of phase-controlled class E inverter with asymmetric circuit configuration. In: IEEE Transactions on Circuits and Systems II: Express Briefs. 2004 ; Vol. 51, No. 10. pp. 523-528.
@article{3ade8339e7d34ad5831218d1a11aa3e8,
title = "Design of phase-controlled class E inverter with asymmetric circuit configuration",
abstract = "A design of phase-controlled class E inverter with asymmetric circuit configuration is presented. By using the presented design method, it is possible to derive the design values, which let the inverters achieve zero-voltage switching continuously in the control range, are derived. By carrying out circuit experiments, it is verified that the experimental results agree with numerical predictions quantitatively, and the validity of the presented design procedure is denoted.",
author = "Daisuke Kawamoto and Hiroo Sekiya and Hirotaka Koizumi and Iwao Sasase and Shinsaku Mori",
year = "2004",
month = "10",
doi = "10.1109/TCSII.2004.834546",
language = "English",
volume = "51",
pages = "523--528",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1057-7130",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - Design of phase-controlled class E inverter with asymmetric circuit configuration

AU - Kawamoto, Daisuke

AU - Sekiya, Hiroo

AU - Koizumi, Hirotaka

AU - Sasase, Iwao

AU - Mori, Shinsaku

PY - 2004/10

Y1 - 2004/10

N2 - A design of phase-controlled class E inverter with asymmetric circuit configuration is presented. By using the presented design method, it is possible to derive the design values, which let the inverters achieve zero-voltage switching continuously in the control range, are derived. By carrying out circuit experiments, it is verified that the experimental results agree with numerical predictions quantitatively, and the validity of the presented design procedure is denoted.

AB - A design of phase-controlled class E inverter with asymmetric circuit configuration is presented. By using the presented design method, it is possible to derive the design values, which let the inverters achieve zero-voltage switching continuously in the control range, are derived. By carrying out circuit experiments, it is verified that the experimental results agree with numerical predictions quantitatively, and the validity of the presented design procedure is denoted.

UR - http://www.scopus.com/inward/record.url?scp=7544242272&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=7544242272&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2004.834546

DO - 10.1109/TCSII.2004.834546

M3 - Article

AN - SCOPUS:7544242272

VL - 51

SP - 523

EP - 528

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1057-7130

IS - 10

ER -