Design of resource sharing reconfigurable ΔΣ SAR-ADC

Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper presents an ADC with re-configurability between SAR-only mode and delta-sigma (ΔΣ assisted mode). The ΔΣ assisted mode brings resolution enhancement. Proposed ADC shares a capacitor array for SAR, feedback DAC, and integrator capacitor in ΔΣ loop, which can reduce the circuit size. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at 32 MS/s and power consumption of 0.55 mW. The SNDR is improved to 62.9 dB by ΔΣ assisted mode.

    Original languageEnglish
    Title of host publicationASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages317-318
    Number of pages2
    Volume2018-January
    ISBN (Electronic)9781509006021
    DOIs
    Publication statusPublished - 2018 Feb 20
    Event23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
    Duration: 2018 Jan 222018 Jan 25

    Other

    Other23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
    CountryKorea, Republic of
    CityJeju
    Period18/1/2218/1/25

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

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  • Cite this

    Ishizuka, M., Yamada, K., & Ishikuro, H. (2018). Design of resource sharing reconfigurable ΔΣ SAR-ADC. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (Vol. 2018-January, pp. 317-318). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297338