The increase of the number of intellectual property (IP) cores integrated on Systems-on-a-Chips (SoCs) will open the way for the further sophisticated SoCs. Networks-on-Chips (NoCs) have been studied as a scalable on-chip interconnect by introducing network structure, which is similar to that in parallel computers. For large NoCs, the size of routing tables cannot be ignored to design a simple router. In this paper, we propose a routing table reduction technique called Destination bundle so as to mitigate the marked increase of routing entries for such routers with minimum entries. In order to shrink routing table, routing entries configured in same router are aggregated into fewer entries by employing the following tunneling mechanism: 1) encapsulation thatprepends routing information of other paths to a packet, and 2) decapsulation that strips it at intermediate routers. Since larger number of encapsulated paths is aggregated into another single path, some routing entries for encapsulated paths can be removed. We apply Destination bundle to the various size of NoCs that ranges from the currently proposed 16-nodes structure to the 512-nodes structure. Simulation results using six application traces show that Destination bundle reduces up to 42.8% of routing entries in the NoCs with 512 nodes.