Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Toshinori Numata; Ken Uchida; Junji Koga; Shin Ichi Takagi

doi:10.1109/soi.2002.1044467

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Toshinori Numata, Ken Uchida, Junji Koga, Shin Ichi Takagi

Research output: Contribution to conference › Paper

14 Citations (Scopus)

Abstract

Device design issues regarding threshold voltage (V_th) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the V_th adjustment method, the combination of back gate bias (V_g2) and gate work function (Φ_m) control is found to provide superior SCE, V_th fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

Original language	English
Pages	179-180
Number of pages	2
DOIs	https://doi.org/10.1109/soi.2002.1044467
Publication status	Published - 2002 Jan 1
Event	IEEE International SOI Conference - Williamsburg, VA, United States Duration: 2002 Oct 7 → 2002 Oct 10

Other

Other	IEEE International SOI Conference
Country	United States
City	Williamsburg, VA
Period	02/10/7 → 02/10/10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Numata, T., Uchida, K., Koga, J., & Takagi, S. I. (2002). Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. 179-180. Paper presented at IEEE International SOI Conference, Williamsburg, VA, United States. https://doi.org/10.1109/soi.2002.1044467

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