Abstract
Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.
| Original language | English |
|---|---|
| Title of host publication | IEEE International SOI Conference |
| Pages | 179-180 |
| Number of pages | 2 |
| Publication status | Published - 2002 |
| Externally published | Yes |
| Event | IEEE International SOI Conference - Williamsburg, VA, United States Duration: 2002 Oct 7 → 2002 Oct 10 |
Other
| Other | IEEE International SOI Conference |
|---|---|
| Country | United States |
| City | Williamsburg, VA |
| Period | 02/10/7 → 02/10/10 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. / Numata, Toshinori; Uchida, Ken; Koga, Junji; Takagi, Shin Ichi.
IEEE International SOI Conference. 2002. p. 179-180.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs
AU - Numata, Toshinori
AU - Uchida, Ken
AU - Koga, Junji
AU - Takagi, Shin Ichi
PY - 2002
Y1 - 2002
N2 - Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.
AB - Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.
UR - http://www.scopus.com/inward/record.url?scp=0036454688&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036454688&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0036454688
SP - 179
EP - 180
BT - IEEE International SOI Conference
ER -