Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Toshinori Numata, Ken Uchida, Junji Koga, Shin Ichi Takagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

Original languageEnglish
Title of host publicationIEEE International SOI Conference
Pages179-180
Number of pages2
Publication statusPublished - 2002
Externally publishedYes
EventIEEE International SOI Conference - Williamsburg, VA, United States
Duration: 2002 Oct 72002 Oct 10

Other

OtherIEEE International SOI Conference
CountryUnited States
CityWilliamsburg, VA
Period02/10/702/10/10

Fingerprint

Threshold voltage
Voltage control
Oxides
Permittivity

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Numata, T., Uchida, K., Koga, J., & Takagi, S. I. (2002). Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. In IEEE International SOI Conference (pp. 179-180)

Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. / Numata, Toshinori; Uchida, Ken; Koga, Junji; Takagi, Shin Ichi.

IEEE International SOI Conference. 2002. p. 179-180.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Numata, T, Uchida, K, Koga, J & Takagi, SI 2002, Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. in IEEE International SOI Conference. pp. 179-180, IEEE International SOI Conference, Williamsburg, VA, United States, 02/10/7.
Numata T, Uchida K, Koga J, Takagi SI. Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. In IEEE International SOI Conference. 2002. p. 179-180
Numata, Toshinori ; Uchida, Ken ; Koga, Junji ; Takagi, Shin Ichi. / Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs. IEEE International SOI Conference. 2002. pp. 179-180
@inproceedings{b1e709816f82425f9cba9463629d8719,
title = "Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs",
abstract = "Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.",
author = "Toshinori Numata and Ken Uchida and Junji Koga and Takagi, {Shin Ichi}",
year = "2002",
language = "English",
pages = "179--180",
booktitle = "IEEE International SOI Conference",

}

TY - GEN

T1 - Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

AU - Numata, Toshinori

AU - Uchida, Ken

AU - Koga, Junji

AU - Takagi, Shin Ichi

PY - 2002

Y1 - 2002

N2 - Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

AB - Device design issues regarding threshold voltage (Vth) control, short channel effects (SCE) and subthreshold slope are qantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (Vg2) and gate work function (Φm) control is found to provide superior SCE, Vth fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.

UR - http://www.scopus.com/inward/record.url?scp=0036454688&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036454688&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0036454688

SP - 179

EP - 180

BT - IEEE International SOI Conference

ER -