Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits

Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura

Research output: Contribution to journalArticle

Abstract

To realize high-resolution pipelined and pipelined-SAR analog-to-digital-converters (ADCs), an accurate residue amplifier is necessary. However, realizing such an amplifier in scaled CMOS is challenging due to the worsened transistor characteristics. Prior works focused on gain calibration techniques to mitigate the use of low-gain amplifiers, in return of system complexity and prolonged startups. In this paper, we introduce a digital amplifier (DA) technique to realize power-efficient and accurate amplification in scaled CMOS. DA cancels out all errors (i.e., gain error, nonlinearity, incomplete settling, power supply noise, and thermal noise) of the low-gain amplifier by feedback based on successive approximation. The DA accuracy can be arbitrary set by configuring the number of bits in the DA capacitor digital-to-analog-converter; the amplifier gain is decoupled from the transistor intrinsic gain which is suitable for scaled CMOS integration. We also show that the power efficiency can be enhanced over conventional opamp-based designs with relaxed settling error requirements of DA-based multiplying digital-to-analog-converters (MDACs). Moreover, the circuit design of DA-based MDACs is further discussed. Measurement results of the calibration-free 0.7-V 12-bit 160-MS/s pipelined-SAR ADC implemented in 28-nm CMOS are reported. Without calibration, the ADC achieves signal-to-noise-and-distortion-ratio = 61.1 dB, figure-of-merit = 12.8 fJ/conv., which is over 3× improvement compared with conventional calibration-free high-speed pipelined ADCs. In addition, we evaluate the DA's process scalability by comparing the measured results of the DA-based MDAC prototyped in 65-and 28-nm CMOS. We observe 2×-3× improvement in speed, power, and area mainly resulting from the DA's process scalability.

Original languageEnglish
Article number8760584
Pages (from-to)2575-2586
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number11
DOIs
Publication statusPublished - 2019 Nov

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Keywords

  • Analog-digital conversion
  • CMOS process scalable
  • digital amplifier (DA)
  • pipelined-SAR analog-to-digital-converter (ADC)
  • switched capacitor (SC) circuit

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yoshioka, K., Sugimoto, T., Waki, N., Kim, S., Kurose, D., Ishii, H., Furuta, M., Sai, A., Ishikuro, H., & Itakura, T. (2019). Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(11), 2575-2586. [8760584]. https://doi.org/10.1109/TVLSI.2019.2924686