Distributed shared memory architecture for JUMP-1: A general-purpose MPP prototype

Takashi Matsumoto, Tomohiro Kudoh, Katsunobu Nishimura, Kei Hiraki, Hideharu Amano, Hidehiko Tanaka

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Abstract

We describe and evaluate a novel distributed-shared memory (DSM) architecture of JUMP-1, a general-purpose MPP system. For improving performance, JUMP-1 DSM architecture utilize cooperation of the network, construction of memory-directories and memory-protocol that unifies memory-consistency, communication and synchronization. Among features of JUMP-1 DSM, we show detail of Reduced Hierarchical Bit-map Directory schemes (RHBDs) which utilizes hierarchy embedded in the interconnection network for reducing network traffic on shared memory operations. Three variations of the RHBD are implemented on a network called the RDT (Recursive Diagonal Torus) consisting of the hierarchical structure of two dimensional tori. In RHBDs, the bit map directory is reduced for quick multicasting without accessing directory in each hierarchy. Most of unnecessary packets caused by reduction of the bit map are removed with the pruning cache provided in the router. The results of simulation demonstrates that latency for cache coherent messages is much improved compared with traditional directory schemes.

Original languageEnglish
Pages131-137
Number of pages7
Publication statusPublished - 1996 Jan 1
Externally publishedYes
EventProceedings of the 1996 2nd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN - Beijing, China
Duration: 1996 Jun 121996 Jun 14

Other

OtherProceedings of the 1996 2nd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN
CityBeijing, China
Period96/6/1296/6/14

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Matsumoto, T., Kudoh, T., Nishimura, K., Hiraki, K., Amano, H., & Tanaka, H. (1996). Distributed shared memory architecture for JUMP-1: A general-purpose MPP prototype. 131-137. Paper presented at Proceedings of the 1996 2nd International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN, Beijing, China, .