DSP-TYPE FIRST-ORDER DIGITAL PHASE-LOCKED LOOP USING LINEAR PHASE DETECTOR.

Masafumi Hagiwara, Masao Nakagawa

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

With the development of modern digital technology, phase-locked loops (PLL) are also becoming digitalized. The digital signal processing (DSP)-type digital PLL (DPLL) realized by microprocessors and software deserves particular interest. This paper proposes a new DSP-type DPLL. This DPLL applies subtraction instead of multiplication in the phase detector to eliminate high-frequency components. In this way the phase detection is linear and does not produce distortion components. Furthermore, it has an AM suppression effect and therefore automatic gain control (AGC) circuit is not needed.

Original languageEnglish
Pages (from-to)99-107
Number of pages9
JournalElectronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume69
Issue number6
Publication statusPublished - 1986 Jun

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Phase locked loops
Digital signal processing
Detectors
Gain control
Microprocessor chips
Networks (circuits)

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

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abstract = "With the development of modern digital technology, phase-locked loops (PLL) are also becoming digitalized. The digital signal processing (DSP)-type digital PLL (DPLL) realized by microprocessors and software deserves particular interest. This paper proposes a new DSP-type DPLL. This DPLL applies subtraction instead of multiplication in the phase detector to eliminate high-frequency components. In this way the phase detection is linear and does not produce distortion components. Furthermore, it has an AM suppression effect and therefore automatic gain control (AGC) circuit is not needed.",
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AB - With the development of modern digital technology, phase-locked loops (PLL) are also becoming digitalized. The digital signal processing (DSP)-type digital PLL (DPLL) realized by microprocessors and software deserves particular interest. This paper proposes a new DSP-type DPLL. This DPLL applies subtraction instead of multiplication in the phase detector to eliminate high-frequency components. In this way the phase detection is linear and does not produce distortion components. Furthermore, it has an AM suppression effect and therefore automatic gain control (AGC) circuit is not needed.

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