DSP‐type first‐order digital phase‐locked loop using linear phase detector

With the development of modern digital technology, phase‐locked loops (PLL) are also becoming digitalized. The digital signal processing (DSP)‐type digital PLL (DPLL) realized by microprocessors and software deserves particular interest. This is because it can be used in time‐sharing operation and its characteristics can easily be controlled. Therefore, it will probably be used widely in digital communication for synchronization and signal conversion circuits. However, up to now, the DSP‐type DPLL has been derived from an analog PLL by directly realizing its operation with DSP methods. Consequently, the generation of distortion components due to the nonlinear characteristic of the phase detection can not be avoided. Moreover, the high‐frequency components arising from the multiplication in the phase detector have a harmful influence on DPLL operation. This paper proposes a new DSP‐type DPLL which eliminates the forementioned disadvantages. This DPLL applies subtraction instead of multiplication in the phase detector to eliminate high‐frequency components. In this way the phase detection linear and does not produce distortion components. Furthermore, it has an AM suppression effect and therefore automatic gain control (AGC) circuit is not needed.