Dynamic deficit round-robin scheduler for 5-Tb/s switch using wavelength routing

K. Yamakoshi, E. Oki, N. Yamanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A dynamic deficit round-robin (DDRR) scheduling scheme for a 5-Tb/s switch is proposed. DDRR is a DRR-based packet scheduler and it can satisfy the max-min fair share. However, DRR cannot satisfy both high throughput and delay requirements. DDRR resolves the problem by changing the granularity for deficit counters according to the packet lengths at queue heads. Simulation results showing the efficiency of DDRR are presented and an implementation of DDRR for the switch is also described.

Original languageEnglish
Title of host publicationHPSR 2002 - Workshop on High Performance Switching and Routing
Subtitle of host publicationMerging Optical and IP Technologies, Proceedings
PublisherIEEE Computer Society
Pages204-208
Number of pages5
ISBN (Print)488552184X, 9784885521843
DOIs
Publication statusPublished - 2002 Jan 1
Externally publishedYes
Event2002 Workshop on High Performance Switching and Routing: Merging Optical and IP Technologies, HPSR 2002 - Kobe, Japan
Duration: 2002 May 262002 May 29

Publication series

NameIEEE International Conference on High Performance Switching and Routing, HPSR
ISSN (Print)2325-5595
ISSN (Electronic)2325-5609

Other

Other2002 Workshop on High Performance Switching and Routing: Merging Optical and IP Technologies, HPSR 2002
CountryJapan
CityKobe
Period02/5/2602/5/29

Keywords

  • DRR
  • deficit
  • delay
  • packet
  • scheduler
  • switch

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Yamakoshi, K., Oki, E., & Yamanaka, N. (2002). Dynamic deficit round-robin scheduler for 5-Tb/s switch using wavelength routing. In HPSR 2002 - Workshop on High Performance Switching and Routing: Merging Optical and IP Technologies, Proceedings (pp. 204-208). [1024236] (IEEE International Conference on High Performance Switching and Routing, HPSR). IEEE Computer Society. https://doi.org/10.1109/HPSR.2002.1024236