Dynamic instruction cascading on GALS microprocessors

Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by generation, GloballyAsynchronous Locally-Synchronous (GALS) designs are an alternative approach to the conventional synchronous processors. In this paper, we propose Dynamic Instruction Cascading (DIG). DIG is a technique to execute two dependent instructions in one cycle by scaling down the clock frequency. Lowering the clock frequency enables the signal to reach farther, thereby computing two instructions in one cycle becomes possible. DIG is effectively applied to GALS processors because lowering only the clock frequency of the target domain is needed and therefore unwanted performance degradation will be prevented. The results showed average performance improvement of 7% on SPEC CPU2000 Integer and MediaBench applications when assuming that DIG is possible by lowering the clock frequency to 80%.

Original languageEnglish
Title of host publicationIntegrated Circuit and System Design
Subtitle of host publicationPower and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings
PublisherSpringer Verlag
Pages30-39
Number of pages10
ISBN (Print)3540290133, 9783540290131
DOIs
Publication statusPublished - 2005
Externally publishedYes
Event15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005 - Leuven, Belgium
Duration: 2005 Sep 202005 Sep 23

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3728 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005
Country/TerritoryBelgium
CityLeuven
Period05/9/2005/9/23

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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