Dynamic instruction cascading on GALS microprocessors

Hiroshi Sasaki; Masaaki Kondo; Hiroshi Nakamura

doi:10.1007/11556930_4

Dynamic instruction cascading on GALS microprocessors

Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by generation, GloballyAsynchronous Locally-Synchronous (GALS) designs are an alternative approach to the conventional synchronous processors. In this paper, we propose Dynamic Instruction Cascading (DIG). DIG is a technique to execute two dependent instructions in one cycle by scaling down the clock frequency. Lowering the clock frequency enables the signal to reach farther, thereby computing two instructions in one cycle becomes possible. DIG is effectively applied to GALS processors because lowering only the clock frequency of the target domain is needed and therefore unwanted performance degradation will be prevented. The results showed average performance improvement of 7% on SPEC CPU2000 Integer and MediaBench applications when assuming that DIG is possible by lowering the clock frequency to 80%.

Original language	English
Title of host publication	Integrated Circuit and System Design
Subtitle of host publication	Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings
Publisher	Springer Verlag
Pages	30-39
Number of pages	10
ISBN (Print)	3540290133, 9783540290131
DOIs	https://doi.org/10.1007/11556930_4
Publication status	Published - 2005
Externally published	Yes
Event	15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005 - Leuven, Belgium Duration: 2005 Sept 20 → 2005 Sept 23

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	3728 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005
Country/Territory	Belgium
City	Leuven
Period	05/9/20 → 05/9/23

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/11556930_4

Cite this

Sasaki, H., Kondo, M., & Nakamura, H. (2005). Dynamic instruction cascading on GALS microprocessors. In Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings (pp. 30-39). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3728 LNCS). Springer Verlag. https://doi.org/10.1007/11556930_4

Dynamic instruction cascading on GALS microprocessors. / Sasaki, Hiroshi; Kondo, Masaaki; Nakamura, Hiroshi.
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Springer Verlag, 2005. p. 30-39 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3728 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sasaki, H, Kondo, M & Nakamura, H 2005, Dynamic instruction cascading on GALS microprocessors. in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3728 LNCS, Springer Verlag, pp. 30-39, 15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005, Leuven, Belgium, 05/9/20. https://doi.org/10.1007/11556930_4

Sasaki H, Kondo M, Nakamura H. Dynamic instruction cascading on GALS microprocessors. In Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Springer Verlag. 2005. p. 30-39. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/11556930_4

Sasaki, Hiroshi ; Kondo, Masaaki ; Nakamura, Hiroshi. / Dynamic instruction cascading on GALS microprocessors. Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 15th International Workshop, PATMOS 2005, Proceedings. Springer Verlag, 2005. pp. 30-39 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{9df6943b111e4564adb0f67e74efc59b,

title = "Dynamic instruction cascading on GALS microprocessors",

abstract = "As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by generation, GloballyAsynchronous Locally-Synchronous (GALS) designs are an alternative approach to the conventional synchronous processors. In this paper, we propose Dynamic Instruction Cascading (DIG). DIG is a technique to execute two dependent instructions in one cycle by scaling down the clock frequency. Lowering the clock frequency enables the signal to reach farther, thereby computing two instructions in one cycle becomes possible. DIG is effectively applied to GALS processors because lowering only the clock frequency of the target domain is needed and therefore unwanted performance degradation will be prevented. The results showed average performance improvement of 7% on SPEC CPU2000 Integer and MediaBench applications when assuming that DIG is possible by lowering the clock frequency to 80%.",

author = "Hiroshi Sasaki and Masaaki Kondo and Hiroshi Nakamura",

year = "2005",

doi = "10.1007/11556930_4",

language = "English",

isbn = "3540290133",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "30--39",

booktitle = "Integrated Circuit and System Design",

note = "15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005 ; Conference date: 20-09-2005 Through 23-09-2005",

}

TY - GEN

T1 - Dynamic instruction cascading on GALS microprocessors

AU - Sasaki, Hiroshi

AU - Kondo, Masaaki

AU - Nakamura, Hiroshi

PY - 2005

Y1 - 2005

N2 - As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by generation, GloballyAsynchronous Locally-Synchronous (GALS) designs are an alternative approach to the conventional synchronous processors. In this paper, we propose Dynamic Instruction Cascading (DIG). DIG is a technique to execute two dependent instructions in one cycle by scaling down the clock frequency. Lowering the clock frequency enables the signal to reach farther, thereby computing two instructions in one cycle becomes possible. DIG is effectively applied to GALS processors because lowering only the clock frequency of the target domain is needed and therefore unwanted performance degradation will be prevented. The results showed average performance improvement of 7% on SPEC CPU2000 Integer and MediaBench applications when assuming that DIG is possible by lowering the clock frequency to 80%.

AB - As difficulty and the costs of distributing a single global clock throughout a processor is growing generation by generation, GloballyAsynchronous Locally-Synchronous (GALS) designs are an alternative approach to the conventional synchronous processors. In this paper, we propose Dynamic Instruction Cascading (DIG). DIG is a technique to execute two dependent instructions in one cycle by scaling down the clock frequency. Lowering the clock frequency enables the signal to reach farther, thereby computing two instructions in one cycle becomes possible. DIG is effectively applied to GALS processors because lowering only the clock frequency of the target domain is needed and therefore unwanted performance degradation will be prevented. The results showed average performance improvement of 7% on SPEC CPU2000 Integer and MediaBench applications when assuming that DIG is possible by lowering the clock frequency to 80%.

UR - http://www.scopus.com/inward/record.url?scp=33646429178&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646429178&partnerID=8YFLogxK

U2 - 10.1007/11556930_4

DO - 10.1007/11556930_4

M3 - Conference contribution

AN - SCOPUS:33646429178

SN - 3540290133

SN - 9783540290131

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 30

EP - 39

BT - Integrated Circuit and System Design

PB - Springer Verlag

T2 - 15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005

Y2 - 20 September 2005 through 23 September 2005

ER -

Dynamic instruction cascading on GALS microprocessors

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this