Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs

Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Inductive-coupling is yet another 3D integration technique that can be used to stack more than three known-good-dies in a SiP without wire connections. Its power consumed for communication by inductive coupling link is one of big problems. A dynamic on/off link control for topology-agnostic 3D NoC (Network on Chip) architecture using inductive-coupling is proposed. The proposed low-power techniques stop the transistors by cutting off the bias voltage in the transmitter of the wireless vertical links only when their utilization is higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3D NoCs. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 43.8-55.0%, while the average performance overhead is 1.4% in wireless topology-agnostic 3D NoC.

Original languageEnglish
Pages (from-to)27-36
Number of pages10
JournalIPSJ Transactions on System LSI Design Methodology
Volume7
DOIs
Publication statusPublished - 2014 Feb

Fingerprint

Electric power utilization
Telecommunication links
Topology
Bias voltage
Transmitters
Transistors
Wire
Communication
Network-on-chip

Keywords

  • 3D NoCs
  • Inductive-coupling
  • Irregular topology
  • On/off link
  • Wireless

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs. / Zhang, Hao; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 7, 02.2014, p. 27-36.

Research output: Contribution to journalArticle

@article{0ac72a4f24b54285afe23265072904a9,
title = "Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs",
abstract = "Inductive-coupling is yet another 3D integration technique that can be used to stack more than three known-good-dies in a SiP without wire connections. Its power consumed for communication by inductive coupling link is one of big problems. A dynamic on/off link control for topology-agnostic 3D NoC (Network on Chip) architecture using inductive-coupling is proposed. The proposed low-power techniques stop the transistors by cutting off the bias voltage in the transmitter of the wireless vertical links only when their utilization is higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3D NoCs. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 43.8-55.0{\%}, while the average performance overhead is 1.4{\%} in wireless topology-agnostic 3D NoC.",
keywords = "3D NoCs, Inductive-coupling, Irregular topology, On/off link, Wireless",
author = "Hao Zhang and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano",
year = "2014",
month = "2",
doi = "10.2197/ipsjtsldm.7.27",
language = "English",
volume = "7",
pages = "27--36",
journal = "IPSJ Transactions on System LSI Design Methodology",
issn = "1882-6687",
publisher = "Information Processing Society of Japan",

}

TY - JOUR

T1 - Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs

AU - Zhang, Hao

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Amano, Hideharu

PY - 2014/2

Y1 - 2014/2

N2 - Inductive-coupling is yet another 3D integration technique that can be used to stack more than three known-good-dies in a SiP without wire connections. Its power consumed for communication by inductive coupling link is one of big problems. A dynamic on/off link control for topology-agnostic 3D NoC (Network on Chip) architecture using inductive-coupling is proposed. The proposed low-power techniques stop the transistors by cutting off the bias voltage in the transmitter of the wireless vertical links only when their utilization is higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3D NoCs. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 43.8-55.0%, while the average performance overhead is 1.4% in wireless topology-agnostic 3D NoC.

AB - Inductive-coupling is yet another 3D integration technique that can be used to stack more than three known-good-dies in a SiP without wire connections. Its power consumed for communication by inductive coupling link is one of big problems. A dynamic on/off link control for topology-agnostic 3D NoC (Network on Chip) architecture using inductive-coupling is proposed. The proposed low-power techniques stop the transistors by cutting off the bias voltage in the transmitter of the wireless vertical links only when their utilization is higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3D NoCs. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 43.8-55.0%, while the average performance overhead is 1.4% in wireless topology-agnostic 3D NoC.

KW - 3D NoCs

KW - Inductive-coupling

KW - Irregular topology

KW - On/off link

KW - Wireless

UR - http://www.scopus.com/inward/record.url?scp=84894200089&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84894200089&partnerID=8YFLogxK

U2 - 10.2197/ipsjtsldm.7.27

DO - 10.2197/ipsjtsldm.7.27

M3 - Article

AN - SCOPUS:84894200089

VL - 7

SP - 27

EP - 36

JO - IPSJ Transactions on System LSI Design Methodology

JF - IPSJ Transactions on System LSI Design Methodology

SN - 1882-6687

ER -