Dynamic processor throttling for power efficient computations

Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

We propose a novel hardware-based DVS technique called dynamic processor throttling (DPT) for power efficient computations. DPT focuses on the performance balance between the processor and main memory, When a performance imbalance is detected, DPT tries to redress the imbalance by setting the clock frequency and supply voltage of the processor to a well-balanced point. This paper describes the micro-architecture mechanisms of DPT and shows the evaluation results on energy saving and performance compared with a conventional cache-miss-driven DVS technique. The results reveal that DPT can reduce 17% of the energy with a 3.4% performance degradation and DPT surpasses the conventional technique in both performance and energy.

Original languageEnglish
Title of host publicationPower-Aware Computer Systems - 4th International Workshop, PACS 2004, Revised Selected Papers
Pages120-134
Number of pages15
DOIs
Publication statusPublished - 2005
Externally publishedYes
Event4th International Workshop on Power-Aware Computer Systems, PACS 2004 - Portland, OR, United States
Duration: 2004 Dec 52004 Dec 5

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3471 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference4th International Workshop on Power-Aware Computer Systems, PACS 2004
Country/TerritoryUnited States
CityPortland, OR
Period04/12/504/12/5

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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