Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs

R. Kawano, Naoaki Yamanaka, E. Oki, T. Kawamura

Research output: Contribution to journalArticle

Abstract

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4Gbit/s with a large level margin can be attained.

Original languageEnglish
Pages (from-to)1641-1643
Number of pages3
JournalElectronics Letters
Volume34
Issue number17
Publication statusPublished - 1998 Aug 20
Externally publishedYes

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Emitter coupled logic circuits
Multicarrier modulation
Networks (circuits)
Automatic teller machines
Interfaces (computer)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs. / Kawano, R.; Yamanaka, Naoaki; Oki, E.; Kawamura, T.

In: Electronics Letters, Vol. 34, No. 17, 20.08.1998, p. 1641-1643.

Research output: Contribution to journalArticle

Kawano, R, Yamanaka, N, Oki, E & Kawamura, T 1998, 'Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs', Electronics Letters, vol. 34, no. 17, pp. 1641-1643.
Kawano, R. ; Yamanaka, Naoaki ; Oki, E. ; Kawamura, T. / Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs. In: Electronics Letters. 1998 ; Vol. 34, No. 17. pp. 1641-1643.
@article{11600ed4d54647adb5841484c03ad5df,
title = "Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs",
abstract = "A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4Gbit/s with a large level margin can be attained.",
author = "R. Kawano and Naoaki Yamanaka and E. Oki and T. Kawamura",
year = "1998",
month = "8",
day = "20",
language = "English",
volume = "34",
pages = "1641--1643",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "17",

}

TY - JOUR

T1 - Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs

AU - Kawano, R.

AU - Yamanaka, Naoaki

AU - Oki, E.

AU - Kawamura, T.

PY - 1998/8/20

Y1 - 1998/8/20

N2 - A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4Gbit/s with a large level margin can be attained.

AB - A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To improve I/O pin number limits, the single-ended ECL circuit operates with a reference signal directly generated from the input signal itself. The reference level can change dynamically to achieve a larger noise margin for the input signal. Experimental results show that operation up to 3.4Gbit/s with a large level margin can be attained.

UR - http://www.scopus.com/inward/record.url?scp=0032141954&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032141954&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0032141954

VL - 34

SP - 1641

EP - 1643

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 17

ER -