Effect of gate-drain spacing for In_0.52Al_0.48As/ In_0.53Ga_0.47As high electron mobility transistors studied by Monte Carlo simulations

We performed two-dimensional Monte Carlo (MC) simulations of 60-nm-gate InP-based lattice-matched In_0:52Al_0:48As/In _0:53Ga_0:47As high electron mobility transistors (HEMTs) to clarify the effect of the gate-drain spacing L_gd on device performance. The calculated maximum transconductance g_m and cutoff frequency f_T increase with decreasing L_gd down to 50nm, which agrees with experimental values. To explain the increase in g_m and f_T, we obtained electron velocity profiles in the InGaAs channel layer. Electron velocity overshoot under the gate is enhanced with decreasing L_gd. The resulting average electron velocity under the gate increases with decreasing L_gd. The enhancement of the electron velocity overshoot can be explained by using potential profiles in the HEMT. Potential profile under the gate in the InGaAs channel becomes steeper with decreasing L_gd.