Abstract
We have demonstrated the effects of interface traps and defects on the charge retention characteristics in silicon-quantum-dot (Si-QDs)-based metal-oxide-semiconductor (MOS) memory structures. MOS diodes with various interface traps and defects introduced by thermal annealing treatment are investigated using a capacitance-voltage (C-V) measurement technique. The model of deep trapping centers including three-dimensional quantum confinement and Coulomb charge effects has been developed to successfully explain the observed long-term charge retention behaviors.
| Original language | English |
|---|---|
| Pages (from-to) | 425-428 |
| Number of pages | 4 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 38 |
| Issue number | 1 B |
| DOIs | |
| Publication status | Published - 1999 Jan 1 |
| Externally published | Yes |
| Event | Proceedings of the 1998 International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, QDS-98 - Sapporo, Japan Duration: 1998 May 31 → 1998 Jun 4 |
Keywords
- Defect
- Interface trap
- MOS memory
- Silicon quantum dot
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)
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Cite this
Shi, Y., Saito, K., Ishikuro, H., & Hiramoto, T. (1999). Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 38(1 B), 425-428. https://doi.org/10.1143/JJAP.38.425