EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET.

K. Matsumoto, N. Hashizume, N. Atoda, Y. Awano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The substrate current under the channel layer in a sub-micron gate self-aligned GaAs FET is shown by Monte Carlo simulation to be the major cause of the short channel effects. By introducing a p-type layer between the channel layer and the substrate, the short channel effects of the FETs having sub-micron gate length are suppressed significantly.

Original languageEnglish
Title of host publicationInstitute of Physics Conference Series
EditorsB. de Cremoux
Pages515-520
Number of pages6
Edition74
Publication statusPublished - 1985 Dec 1
Externally publishedYes

Publication series

NameInstitute of Physics Conference Series
Number74
ISSN (Print)0373-0751

ASJC Scopus subject areas

  • Physics and Astronomy(all)

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    Matsumoto, K., Hashizume, N., Atoda, N., & Awano, Y. (1985). EFFECTS OF P-TYPE BARRIER LAYER ON CHARACTERISTICS OF SUB-MICRON GATE SELF-ALIGNED GaAs FET. In B. de Cremoux (Ed.), Institute of Physics Conference Series (74 ed., pp. 515-520). (Institute of Physics Conference Series; No. 74).