Enabling circuit-switching in modern on-chip networks

Jinyu Jiao, Yuan He, Thang Cao, Masaaki Kondo

Research output: Contribution to journalArticlepeer-review


Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively.

Original languageEnglish
Article number104712
JournalMicroprocessors and Microsystems
Publication statusPublished - 2022 Nov


  • Circuit switching
  • Energy
  • Hybrid switching
  • Latency
  • On-chip networks
  • Virtual channels

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


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