Energy-efficient dynamic instruction scheduling logic through instruction grouping

Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

Dynamic instruction scheduling logic is quite complex and dissipates significant energy in microprocessors that support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the complexity and energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required number of ports and the size of the structure for dispatch, wakeup, select, and issue. The present paper describes the microarchitecture mechanisms and shows evaluation results for energy savings and performance. These results reveal that the proposed technique can greatly reduce energy with almost no performance degradation, compared to the conventional dynamic instruction scheduling logic.

Original languageEnglish
Title of host publicationISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Pages43-48
Number of pages6
DOIs
Publication statusPublished - 2006
Externally publishedYes
EventISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany
Duration: 2006 Oct 42006 Oct 6

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2006
ISSN (Print)1533-4678

Conference

ConferenceISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
Country/TerritoryGermany
CityTegernsee, Bavaria
Period06/10/406/10/6

Keywords

  • Dynamic instruction scheduling
  • Instruction grouping
  • Issue queue

ASJC Scopus subject areas

  • Engineering(all)

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