Energy efficient network design tool for green IP/Ethernet networks

Hidetoshi Takeshita, Naoaki Yamanaka, Satoru Okamoto, Sho Shimizu, Shan Gao

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

An innovative energy-efficient network design algorithm and a tool to lower the network power consumption are proposed. The goal is an energy efficient network that carries its rated communication load while meeting the QoS requirements by using the minimum set of nodes and links. QoS metrics include hop limit, bandwidth limit reliability and stability. The proposed algorithm addresses the set-covered problem. To discover the optimum network configuration efficiently, we propose a network configuration generation algorithm that utilizes DAPDNA-2, a parallel data flow type reconfigurable processer. The processor automatically produces the node/link set in n-digit binary form where links are modeled as "1" for power on and "0" for power off; it also confirms that the QoS requirements are satisfied. Evaluation results show that DAPDNA-2 is 2-orders faster than the conventional sequential method running on a Pentium-4 processor. Prototype Gigabit Layer-2 switches having remote link power on/off and traffic monitoring functions are developed. Using these switches, we successfully demonstrate an energy efficient IP/Ethernet network. The evaluation results show that network power savings of up to 30% can be realized under the NFSNET topology model. The proposed algorithm and power efficient network architecture can be applied to realize the future green network.

Original languageEnglish
Pages (from-to)264-270
Number of pages7
JournalOptical Switching and Networking
Volume9
Issue number3
DOIs
Publication statusPublished - 2012 Jul 1

    Fingerprint

Keywords

  • Green IT
  • IP/Ethernet
  • Low power consumption
  • PCE
  • Reconfigurable processor
  • Set-covered problem

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this