Enhanced degradation by negative bias temperature stress in Si nanowire transistor

Kensuke Ota, Masumi Saitoh, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

    Research output: Contribution to journalArticle

    6 Citations (Scopus)

    Abstract

    Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

    Original languageEnglish
    Article number02BC08
    JournalJapanese journal of applied physics
    Volume51
    Issue number2 PART 2
    DOIs
    Publication statusPublished - 2012 Feb 1

    ASJC Scopus subject areas

    • Engineering(all)
    • Physics and Astronomy(all)

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  • Cite this

    Ota, K., Saitoh, M., Tanaka, C., Nakabayashi, Y., Uchida, K., & Numata, T. (2012). Enhanced degradation by negative bias temperature stress in Si nanowire transistor. Japanese journal of applied physics, 51(2 PART 2), [02BC08]. https://doi.org/10.1143/JJAP.51.02BC08