Enhanced degradation by negative bias temperature stress in Si nanowire transistor

Kensuke Ota, Masumi Saitoh, Chika Tanaka, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

Original languageEnglish
Article number02BC08
JournalJapanese Journal of Applied Physics
Volume51
Issue number2 PART 2
DOIs
Publication statusPublished - 2012 Feb
Externally publishedYes

Fingerprint

Nanowires
Transistors
nanowires
transistors
degradation
Degradation
Threshold voltage
threshold voltage
Temperature
temperature
shift
recovery
Electric fields
high speed
traps
Recovery
electric fields

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Ota, K., Saitoh, M., Tanaka, C., Nakabayashi, Y., Uchida, K., & Numata, T. (2012). Enhanced degradation by negative bias temperature stress in Si nanowire transistor. Japanese Journal of Applied Physics, 51(2 PART 2), [02BC08]. https://doi.org/10.1143/JJAP.51.02BC08

Enhanced degradation by negative bias temperature stress in Si nanowire transistor. / Ota, Kensuke; Saitoh, Masumi; Tanaka, Chika; Nakabayashi, Yukio; Uchida, Ken; Numata, Toshinori.

In: Japanese Journal of Applied Physics, Vol. 51, No. 2 PART 2, 02BC08, 02.2012.

Research output: Contribution to journalArticle

Ota, K, Saitoh, M, Tanaka, C, Nakabayashi, Y, Uchida, K & Numata, T 2012, 'Enhanced degradation by negative bias temperature stress in Si nanowire transistor', Japanese Journal of Applied Physics, vol. 51, no. 2 PART 2, 02BC08. https://doi.org/10.1143/JJAP.51.02BC08
Ota, Kensuke ; Saitoh, Masumi ; Tanaka, Chika ; Nakabayashi, Yukio ; Uchida, Ken ; Numata, Toshinori. / Enhanced degradation by negative bias temperature stress in Si nanowire transistor. In: Japanese Journal of Applied Physics. 2012 ; Vol. 51, No. 2 PART 2.
@article{dae23ca4a5ee4a46a589e548188603cb,
title = "Enhanced degradation by negative bias temperature stress in Si nanowire transistor",
abstract = "Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.",
author = "Kensuke Ota and Masumi Saitoh and Chika Tanaka and Yukio Nakabayashi and Ken Uchida and Toshinori Numata",
year = "2012",
month = "2",
doi = "10.1143/JJAP.51.02BC08",
language = "English",
volume = "51",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "2 PART 2",

}

TY - JOUR

T1 - Enhanced degradation by negative bias temperature stress in Si nanowire transistor

AU - Ota, Kensuke

AU - Saitoh, Masumi

AU - Tanaka, Chika

AU - Nakabayashi, Yukio

AU - Uchida, Ken

AU - Numata, Toshinori

PY - 2012/2

Y1 - 2012/2

N2 - Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

AB - Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

UR - http://www.scopus.com/inward/record.url?scp=84857473709&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84857473709&partnerID=8YFLogxK

U2 - 10.1143/JJAP.51.02BC08

DO - 10.1143/JJAP.51.02BC08

M3 - Article

AN - SCOPUS:84857473709

VL - 51

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 2 PART 2

M1 - 02BC08

ER -