Evaluation of a multicore reconfigurable architecture with variable core sizes

Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A multicore architecture for processors has emerged as a dominant trend in the chip making industry. As reconfigurable devices gradually prove their capability in improving computation power while preserving flexibility, we are examining a multicore reconfigurable architecture consisting ofmultiple reconfigurable computational cores connected by an interconnection network. Using an NEe Electronics' DRP-l as a core for the multicore architecture, a comparison with a tile-based architecture is performed by implementing several streaming applications with various versions. By using wider communication channels and assigning more resources for computations, it is possible to improve throughput over implementations for the tile-based architecture. Another evaluation with different core sizes is examined in order to see the effect of core size in a homogeneous multicore system on performance and internal fragmentation. Evaluation results show that the size ofcore is a trade-offbetween throughput and resource usage.

Original languageEnglish
Title of host publicationIPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium
DOIs
Publication statusPublished - 2009
Event23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 - Rome, Italy
Duration: 2009 May 232009 May 29

Other

Other23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009
CountryItaly
CityRome
Period09/5/2309/5/29

Fingerprint

Reconfigurable architectures
Tile
Throughput
Electronic equipment
Industry

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software

Cite this

Tuan, V. M., Katsura, N., Matsutani, H., & Amano, H. (2009). Evaluation of a multicore reconfigurable architecture with variable core sizes. In IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium [5161225] https://doi.org/10.1109/IPDPS.2009.5161225

Evaluation of a multicore reconfigurable architecture with variable core sizes. / Tuan, Vu Manh; Katsura, Naohiro; Matsutani, Hiroki; Amano, Hideharu.

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 2009. 5161225.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tuan, VM, Katsura, N, Matsutani, H & Amano, H 2009, Evaluation of a multicore reconfigurable architecture with variable core sizes. in IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium., 5161225, 23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009, Rome, Italy, 09/5/23. https://doi.org/10.1109/IPDPS.2009.5161225
Tuan VM, Katsura N, Matsutani H, Amano H. Evaluation of a multicore reconfigurable architecture with variable core sizes. In IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 2009. 5161225 https://doi.org/10.1109/IPDPS.2009.5161225
Tuan, Vu Manh ; Katsura, Naohiro ; Matsutani, Hiroki ; Amano, Hideharu. / Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 2009.
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