Evaluation of cache base network processor by using real backbone network trace

Shinichi Ishida, Michitaka Okuno, Hiroaki Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper a novel cache-based packet-processing-engine (PPE) architecture that achieves high packet-processing throughput with low-power consumption is proposed and evaluated. As network packets of the same header information appear repeatedly in a short time, a special cache, the so called header-learning cache(HLC), memorizes the packet-processing method and enables most packets to skip the execution at the processing units array. The implementation of the cache-based PPE architecture, P-Gear, was designed. Real backbone network trace was used to evaluate the performance of it. This P-Gear can achieve over 80% cache hit rate using 4K/32K entry for access/core networks. Compared to conventional PPE, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.6% of the power consumption required by the conventional PPE.

Original languageEnglish
Title of host publication2006 Workshop on High Performance Switching and Routing, HPSR 2006
Pages49-54
Number of pages6
Publication statusPublished - 2006
Event2006 Workshop on High Performance Switching and Routing, HPSR 2006 - Poznan, Poland
Duration: 2006 Jun 72006 Jun 9

Other

Other2006 Workshop on High Performance Switching and Routing, HPSR 2006
CountryPoland
CityPoznan
Period06/6/706/6/9

Fingerprint

Network Processor
Backbone
Cache
Trace
Evaluation
Processing
Engine
Engines
Gears
Power Consumption
Electric power utilization
Throughput
Packet networks
Hits
Die
Unit
Evaluate

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Theoretical Computer Science

Cite this

Ishida, S., Okuno, M., & Nishi, H. (2006). Evaluation of cache base network processor by using real backbone network trace. In 2006 Workshop on High Performance Switching and Routing, HPSR 2006 (pp. 49-54). [1709680]

Evaluation of cache base network processor by using real backbone network trace. / Ishida, Shinichi; Okuno, Michitaka; Nishi, Hiroaki.

2006 Workshop on High Performance Switching and Routing, HPSR 2006. 2006. p. 49-54 1709680.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishida, S, Okuno, M & Nishi, H 2006, Evaluation of cache base network processor by using real backbone network trace. in 2006 Workshop on High Performance Switching and Routing, HPSR 2006., 1709680, pp. 49-54, 2006 Workshop on High Performance Switching and Routing, HPSR 2006, Poznan, Poland, 06/6/7.
Ishida S, Okuno M, Nishi H. Evaluation of cache base network processor by using real backbone network trace. In 2006 Workshop on High Performance Switching and Routing, HPSR 2006. 2006. p. 49-54. 1709680
Ishida, Shinichi ; Okuno, Michitaka ; Nishi, Hiroaki. / Evaluation of cache base network processor by using real backbone network trace. 2006 Workshop on High Performance Switching and Routing, HPSR 2006. 2006. pp. 49-54
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