Evaluation of errors in feedback control based on persistence prediction in model-based process controller system for deep sub-100 nm gate fabrication

Takeshi K. Goto, Toshiaki Makabe

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Using model-based advanced process control (APC) in the gate etching process, gate linewidth variations that are caused by variations in the photo resist linewidth are reduced by feedforward control of the photo resist linewidth that is obtained by a critical dimension (CD) measurement tool. Both long-term process drift in the etching process and long-term instability of the CD measurement tool lead to variations in the process model for APC. These process model variations result in gate linewidth variations and are attenuated by feedback control using the etch CD bias from the previously processed lot. We used a lot-tolot model-based APC system and a critical dimension scanning electron microscope (CD-SEM) in a deep sub-100nm gate fabrication line to investigate long-term variations in the process model over a period of six months, and to study how much the variations are reduced by feedback control based on persistence prediction methods using the etch CD bias for the pilot wafer from the currently processed lot. The process model uses the linear relationship between the etch CD bias and the gas mixture ratio at the gate linewidth plasma trimming step, and the gradient is almost constant over the term. The spread in the long-term variation in the process model was 8.12nm. The variation mainly included process drift in the plasma etcher, and the persistence of the etch CD bias in the lot after processing was significantly lost beyond approximately one week. When using feedback control based on the persistence prediction method using the etch CD bias for the pilot wafer from the currently processed lot, the standard deviation of the feedback error was 0.50 nm of 1σ On the other hand, when calculating feedback control with the lot-mean etch CD bias from the lot processed immediately before the currently processed lot, the standard deviation of the feedback error was estimated to be 0.82 nm of 1σ When performing feedback with the etching shift value of the pilot wafers, the percentage of lots whose post etch CD value fell within the range of ±1 nm from the target value was higher by 20% than the simulated value of the percentage of lots in which feedback was calculated with the etch CD bias of the previously processed lots.

Original languageEnglish
Pages (from-to)7645-7654
Number of pages10
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume45
Issue number10 A
DOIs
Publication statusPublished - 2006 Oct 15

Keywords

  • Advanced process control (APC)
  • CMOS logic chip
  • Critical dimension (CD)
  • Feedback control
  • Feedforward control
  • Gate fabrication
  • MOSFET
  • Plasma etching

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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