TY - GEN
T1 - Evaluation of MuCCRA-D
T2 - 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
AU - Kato, Masaru
AU - Hasegawa, Yohei
AU - Amano, Hideharu
PY - 2008/12/1
Y1 - 2008/12/1
N2 - Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a typical island-style interconnection in its PE array. Although the island-style interconnection is flexible, the large delay time caused by passing multiple switches and long wires often degrades its clock frequency. In this paper, MuCCRA-D, a dynamically reconfigurable processor which uses direct interconnection between neighboring PEs, is designed and evaluated. The evaluation results show that the required semiconductor area for MuCCRA-D is 12% smaller than that of MuCCRA-1 by reducing wiring resource in the interconnection. Since higher clock frequency can be used, DCT, α-Blending, Bubble-Sort and SHA-1 implemented on the MuCCRA-D are 3.84 times faster than MuCCRA-1 at maximum.
AB - Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a typical island-style interconnection in its PE array. Although the island-style interconnection is flexible, the large delay time caused by passing multiple switches and long wires often degrades its clock frequency. In this paper, MuCCRA-D, a dynamically reconfigurable processor which uses direct interconnection between neighboring PEs, is designed and evaluated. The evaluation results show that the required semiconductor area for MuCCRA-D is 12% smaller than that of MuCCRA-1 by reducing wiring resource in the interconnection. Since higher clock frequency can be used, DCT, α-Blending, Bubble-Sort and SHA-1 implemented on the MuCCRA-D are 3.84 times faster than MuCCRA-1 at maximum.
KW - Dynamically reconfigurable processor
KW - Interconnection network
UR - http://www.scopus.com/inward/record.url?scp=62649162376&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=62649162376&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:62649162376
SN - 1601320647
SN - 9781601320643
T3 - Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
SP - 215
EP - 221
BT - Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Y2 - 14 July 2008 through 17 July 2008
ER -