Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Masaru Kato, Yohei Hasegawa, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project, uses a typical island-style interconnection in its PE array. Although the island-style interconnection is flexible, the large delay time caused by passing multiple switches and long wires often degrades its clock frequency. In this paper, MuCCRA-D, a dynamically reconfigurable processor which uses direct interconnection between neighboring PEs, is designed and evaluated. The evaluation results show that the required semiconductor area for MuCCRA-D is 12% smaller than that of MuCCRA-1 by reducing wiring resource in the interconnection. Since higher clock frequency can be used, DCT, α-Blending, Bubble-Sort and SHA-1 implemented on the MuCCRA-D are 3.84 times faster than MuCCRA-1 at maximum.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Pages215-221
Number of pages7
Publication statusPublished - 2008 Dec 1
Event2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States
Duration: 2008 Jul 142008 Jul 17

Publication series

NameProceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

Other

Other2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
CountryUnited States
CityLas Vegas, NV
Period08/7/1408/7/17

Keywords

  • Dynamically reconfigurable processor
  • Interconnection network

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software

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    Kato, M., Hasegawa, Y., & Amano, H. (2008). Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs. In Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 (pp. 215-221). (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).