Evaluation of network interface controller on DIMMnet-2 prototype board

Akira Kitamura, Yoshihiro Hamada, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot by using the indirect accessing to memory and buffers. Although the current board is a prototype using an FPGA, the latency for 8 Bytes data transfer is only 0.441μs.

Original languageEnglish
Title of host publicationProceedings - Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005
Pages778-780
Number of pages3
DOIs
Publication statusPublished - 2005 Dec 1
Event6th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005 - Dalian, China
Duration: 2005 Dec 52005 Dec 8

Publication series

NameParallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings
Volume2005

Other

Other6th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005
CountryChina
CityDalian
Period05/12/505/12/8

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Science Applications

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