Evaluation of network interface controller on DIMMnet-2 prototype board

Akira Kitamura, Yoshihiro Hamada, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot by using the indirect accessing to memory and buffers. Although the current board is a prototype using an FPGA, the latency for 8 Bytes data transfer is only 0.441μs.

Original languageEnglish
Title of host publicationParallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings
Pages778-780
Number of pages3
Volume2005
DOIs
Publication statusPublished - 2005
Event6th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005 - Dalian, China
Duration: 2005 Dec 52005 Dec 8

Other

Other6th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005
CountryChina
CityDalian
Period05/12/505/12/8

Fingerprint

Interfaces (computer)
Controllers
Data storage equipment
Data transfer
Field programmable gate arrays (FPGA)

ASJC Scopus subject areas

  • Computer Networks and Communications

Cite this

Kitamura, A., Hamada, Y., Miyabe, Y., Izawa, T., Miyashiro, T., Watanabe, K., ... Amano, H. (2005). Evaluation of network interface controller on DIMMnet-2 prototype board. In Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings (Vol. 2005, pp. 778-780). [1579028] https://doi.org/10.1109/PDCAT.2005.136

Evaluation of network interface controller on DIMMnet-2 prototype board. / Kitamura, Akira; Hamada, Yoshihiro; Miyabe, Yasuo; Izawa, Tetsu; Miyashiro, Tomotaka; Watanabe, Konosuke; Otsuka, Tomohiro; Tanabe, Noboru; Nakajo, Hironori; Amano, Hideharu.

Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings. Vol. 2005 2005. p. 778-780 1579028.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kitamura, A, Hamada, Y, Miyabe, Y, Izawa, T, Miyashiro, T, Watanabe, K, Otsuka, T, Tanabe, N, Nakajo, H & Amano, H 2005, Evaluation of network interface controller on DIMMnet-2 prototype board. in Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings. vol. 2005, 1579028, pp. 778-780, 6th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005, Dalian, China, 05/12/5. https://doi.org/10.1109/PDCAT.2005.136
Kitamura A, Hamada Y, Miyabe Y, Izawa T, Miyashiro T, Watanabe K et al. Evaluation of network interface controller on DIMMnet-2 prototype board. In Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings. Vol. 2005. 2005. p. 778-780. 1579028 https://doi.org/10.1109/PDCAT.2005.136
Kitamura, Akira ; Hamada, Yoshihiro ; Miyabe, Yasuo ; Izawa, Tetsu ; Miyashiro, Tomotaka ; Watanabe, Konosuke ; Otsuka, Tomohiro ; Tanabe, Noboru ; Nakajo, Hironori ; Amano, Hideharu. / Evaluation of network interface controller on DIMMnet-2 prototype board. Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings. Vol. 2005 2005. pp. 778-780
@inproceedings{c3022903ae414d91b52582285a2ecf4a,
title = "Evaluation of network interface controller on DIMMnet-2 prototype board",
abstract = "By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot by using the indirect accessing to memory and buffers. Although the current board is a prototype using an FPGA, the latency for 8 Bytes data transfer is only 0.441μs.",
author = "Akira Kitamura and Yoshihiro Hamada and Yasuo Miyabe and Tetsu Izawa and Tomotaka Miyashiro and Konosuke Watanabe and Tomohiro Otsuka and Noboru Tanabe and Hironori Nakajo and Hideharu Amano",
year = "2005",
doi = "10.1109/PDCAT.2005.136",
language = "English",
isbn = "0769524052",
volume = "2005",
pages = "778--780",
booktitle = "Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings",

}

TY - GEN

T1 - Evaluation of network interface controller on DIMMnet-2 prototype board

AU - Kitamura, Akira

AU - Hamada, Yoshihiro

AU - Miyabe, Yasuo

AU - Izawa, Tetsu

AU - Miyashiro, Tomotaka

AU - Watanabe, Konosuke

AU - Otsuka, Tomohiro

AU - Tanabe, Noboru

AU - Nakajo, Hironori

AU - Amano, Hideharu

PY - 2005

Y1 - 2005

N2 - By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot by using the indirect accessing to memory and buffers. Although the current board is a prototype using an FPGA, the latency for 8 Bytes data transfer is only 0.441μs.

AB - By recent performance improvement of interconnection networks for a PC cluster, standard I/O bus which connects network interface becomes the performance bottleneck. DIMMnet is a network interface which can solve the problem by using the memory bus instead of PCI bus or other I/O buses. The second generation network interface DIMMnet-2 can be connected with DDR-SDRAM slot by using the indirect accessing to memory and buffers. Although the current board is a prototype using an FPGA, the latency for 8 Bytes data transfer is only 0.441μs.

UR - http://www.scopus.com/inward/record.url?scp=33745147554&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33745147554&partnerID=8YFLogxK

U2 - 10.1109/PDCAT.2005.136

DO - 10.1109/PDCAT.2005.136

M3 - Conference contribution

AN - SCOPUS:33745147554

SN - 0769524052

SN - 9780769524054

VL - 2005

SP - 778

EP - 780

BT - Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings

ER -