Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

Original languageEnglish
Title of host publicationProceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages41-48
Number of pages8
ISBN (Print)9781479986699
DOIs
Publication statusPublished - 2015 Nov 11
Event9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 - Turin, Italy
Duration: 2015 Sep 232015 Sep 25

Other

Other9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
CountryItaly
CityTurin
Period15/9/2315/9/25

    Fingerprint

Keywords

  • Inductive coupling interconnect
  • Interconnection network

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M., & Amano, H. (2015). Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. In Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 (pp. 41-48). [7328185] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2015.26