Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

Original languageEnglish
Title of host publicationProceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages41-48
Number of pages8
ISBN (Print)9781479986699
DOIs
Publication statusPublished - 2015 Nov 11
Event9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 - Turin, Italy
Duration: 2015 Sep 232015 Sep 25

Other

Other9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
CountryItaly
CityTurin
Period15/9/2315/9/25

Fingerprint

Large scale systems
Costs
Masks
Communication
System-on-chip

Keywords

  • Inductive coupling interconnect
  • Interconnection network

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M., & Amano, H. (2015). Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. In Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 (pp. 41-48). [7328185] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2015.26

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. / Nakahara, Hiroshi; Ozaki, Tomoya; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 41-48 7328185.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakahara, H, Ozaki, T, Matsutani, H, Koibuchi, M & Amano, H 2015, Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. in Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015., 7328185, Institute of Electrical and Electronics Engineers Inc., pp. 41-48, 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, Turin, Italy, 15/9/23. https://doi.org/10.1109/MCSoC.2015.26
Nakahara H, Ozaki T, Matsutani H, Koibuchi M, Amano H. Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. In Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 41-48. 7328185 https://doi.org/10.1109/MCSoC.2015.26
Nakahara, Hiroshi ; Ozaki, Tomoya ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 41-48
@inproceedings{09afe9f3efae4c88ad7078d9d254cf5f,
title = "Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips",
abstract = "The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8{\%} and the performance of NAS Parallel Benchmarks by 6.7{\%} on average compared to that of 2D mesh.",
keywords = "Inductive coupling interconnect, Interconnection network",
author = "Hiroshi Nakahara and Tomoya Ozaki and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano",
year = "2015",
month = "11",
day = "11",
doi = "10.1109/MCSoC.2015.26",
language = "English",
isbn = "9781479986699",
pages = "41--48",
booktitle = "Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

AU - Nakahara, Hiroshi

AU - Ozaki, Tomoya

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Amano, Hideharu

PY - 2015/11/11

Y1 - 2015/11/11

N2 - The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

AB - The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.

KW - Inductive coupling interconnect

KW - Interconnection network

UR - http://www.scopus.com/inward/record.url?scp=84962745983&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84962745983&partnerID=8YFLogxK

U2 - 10.1109/MCSoC.2015.26

DO - 10.1109/MCSoC.2015.26

M3 - Conference contribution

SN - 9781479986699

SP - 41

EP - 48

BT - Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -