Abstract
The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.
Original language | English |
---|---|
Title of host publication | Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 41-48 |
Number of pages | 8 |
ISBN (Print) | 9781479986699 |
DOIs | |
Publication status | Published - 2015 Nov 11 |
Event | 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 - Turin, Italy Duration: 2015 Sep 23 → 2015 Sep 25 |
Other
Other | 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015 |
---|---|
Country | Italy |
City | Turin |
Period | 15/9/23 → 15/9/25 |
Keywords
- Inductive coupling interconnect
- Interconnection network
ASJC Scopus subject areas
- Hardware and Architecture