TY - GEN
T1 - Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips
AU - Nakahara, Hiroshi
AU - Ozaki, Tomoya
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/11/11
Y1 - 2015/11/11
N2 - The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.
AB - The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking. To connect a large number of small chips for building a large scale system, a novel chip stacking method called the staggered stacking is proposed that enables the system to be extended to x and y dimensions, not only to z dimension. For such flexible inter-chip communication, we use Inductive coupling ThruChip Interface (TCI). Here, a novel chip staking layout, and its deadlock-free routing design for the case using multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 6.7% on average compared to that of 2D mesh.
KW - Inductive coupling interconnect
KW - Interconnection network
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U2 - 10.1109/MCSoC.2015.26
DO - 10.1109/MCSoC.2015.26
M3 - Conference contribution
AN - SCOPUS:84962745983
T3 - Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
SP - 41
EP - 48
BT - Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015
Y2 - 23 September 2015 through 25 September 2015
ER -