Experimental evaluation of low power techniques on dependable responsive multithreaded processor

Kazutoshi Suito, Masayoshi Takasu, Rikuhei Ueda, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents experimental evaluations of low power techniques on the D-RMTP (Dependable Responsive Multithreaded Processor) for distributed real-time systems. The D-RMTP has the fine-grained module level low power techniques including DVFS (Dynamic Voltage and Frequency Scaling) and clock gating. In real-time systems, the gain and overheads (voltage and clock transition latencies) must be known beforehand in order to meet time constraints. Thus, detailed analysis using actual equipment is required since these parameters are strongly dependent on the platform. In this paper we analyze a power consumption, a chip temperature, and an overhead when DVFS and clock gating are applied. The experimental results show that the maximum overheads of changing voltage, changing frequency, and clock gating are 75μs, 12μs, and 4μs, respectively. When the DVFS is applied, the power consumption and temperature of the D-RMTP are reduced by 88% and 23% respectively. The power consumption of each hardware module is reduced by approximately 41∼98%. The results obtained by the experiments present a favorable trade-off between the power and temperature reduction and the transition overhead.

Original languageEnglish
Title of host publication28th International Conference on Computers and Their Applications 2013, CATA 2013
Pages281-288
Number of pages8
Publication statusPublished - 2013
Event28th International Conference on Computers and Their Applications 2013, CATA 2013 - Honolulu, HI, United States
Duration: 2013 Mar 42013 Mar 6

Other

Other28th International Conference on Computers and Their Applications 2013, CATA 2013
CountryUnited States
CityHonolulu, HI
Period13/3/413/3/6

Fingerprint

Clocks
Electric power utilization
Real time systems
Electric potential
Temperature
Microprocessor chips
Hardware
Dynamic frequency scaling
Voltage scaling
Experiments

ASJC Scopus subject areas

  • Computer Science Applications

Cite this

Suito, K., Takasu, M., Ueda, R., Fujii, K., Matsutani, H., & Yamasaki, N. (2013). Experimental evaluation of low power techniques on dependable responsive multithreaded processor. In 28th International Conference on Computers and Their Applications 2013, CATA 2013 (pp. 281-288)

Experimental evaluation of low power techniques on dependable responsive multithreaded processor. / Suito, Kazutoshi; Takasu, Masayoshi; Ueda, Rikuhei; Fujii, Kei; Matsutani, Hiroki; Yamasaki, Nobuyuki.

28th International Conference on Computers and Their Applications 2013, CATA 2013. 2013. p. 281-288.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suito, K, Takasu, M, Ueda, R, Fujii, K, Matsutani, H & Yamasaki, N 2013, Experimental evaluation of low power techniques on dependable responsive multithreaded processor. in 28th International Conference on Computers and Their Applications 2013, CATA 2013. pp. 281-288, 28th International Conference on Computers and Their Applications 2013, CATA 2013, Honolulu, HI, United States, 13/3/4.
Suito K, Takasu M, Ueda R, Fujii K, Matsutani H, Yamasaki N. Experimental evaluation of low power techniques on dependable responsive multithreaded processor. In 28th International Conference on Computers and Their Applications 2013, CATA 2013. 2013. p. 281-288
Suito, Kazutoshi ; Takasu, Masayoshi ; Ueda, Rikuhei ; Fujii, Kei ; Matsutani, Hiroki ; Yamasaki, Nobuyuki. / Experimental evaluation of low power techniques on dependable responsive multithreaded processor. 28th International Conference on Computers and Their Applications 2013, CATA 2013. 2013. pp. 281-288
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