TY - JOUR
T1 - Experimental study on deformation potential (Dac) in MOSFETs
T2 - Demonstration of increased Dac at MOS interfaces and its impact on electron mobility
AU - Ohashi, Teruyuki
AU - Tanaka, Takahisa
AU - Takahashi, Tsunaki
AU - Oda, Shunri
AU - Uchida, Ken
N1 - Publisher Copyright:
© 2013 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/9
Y1 - 2016/9
N2 - Deformation potential (Dac), which is one of the most important parameters determining the rate of electronacoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that Dac increases sharply at the MOS interface. To investigate the impact of the increased Dac on μe, thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that μe of greater than 1100 cm2V-1s-1 is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the Dac profile around the MOS interface, experimental μe of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. μe of the body-channel SOI MOSFETs is also well reproduced using the same Dac profile. Thus, it is concluded that Dac increases sharply at the Si/SiO2 interface. The accurate modeling of the increased Dac around the Si/SiO2 interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.
AB - Deformation potential (Dac), which is one of the most important parameters determining the rate of electronacoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that Dac increases sharply at the MOS interface. To investigate the impact of the increased Dac on μe, thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that μe of greater than 1100 cm2V-1s-1 is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the Dac profile around the MOS interface, experimental μe of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. μe of the body-channel SOI MOSFETs is also well reproduced using the same Dac profile. Thus, it is concluded that Dac increases sharply at the Si/SiO2 interface. The accurate modeling of the increased Dac around the Si/SiO2 interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.
KW - Deformation potential
KW - MOSFETs
KW - SOI
KW - acoustic phonon scattering
KW - low-field mobility
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U2 - 10.1109/JEDS.2016.2581217
DO - 10.1109/JEDS.2016.2581217
M3 - Article
AN - SCOPUS:84984669597
VL - 4
SP - 278
EP - 285
JO - IEEE Journal of the Electron Devices Society
JF - IEEE Journal of the Electron Devices Society
SN - 2168-6734
IS - 5
M1 - 7492205
ER -