Exploiting hardware reconfigurability on window join

Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Stream processing is attracting wider attention in recent years, and in order to get high efficiency, more people are now trying to leverage hardware for stream processing. In this paper, we clarify two issues by taking window join as an example application: a) how a software engineer would efficiently utilize hardware, and b) how adaptiveness will be achieved on it. We use a dynamically reconfigurable hardware with a C-based high level synthesis tool as our evaluation platform. The throughput improved by 216 times through software code optimization, and achieved 26 times higher throughput/power efficiency than an optimized software solution for a CPU. We conclude that a software engineer with certain hardware knowledge will be able to facilitate hardware, and dynamic reconfiguration capability improves the throughput/power efficiency of stream processing.

Original languageEnglish
Title of host publicationProceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
Pages690-691
Number of pages2
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013 - Helsinki, Finland
Duration: 2013 Jul 12013 Jul 5

Publication series

NameProceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013

Other

Other2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013
CountryFinland
CityHelsinki
Period13/7/113/7/5

Keywords

  • high level synthesis
  • processor architecture
  • stream processing
  • window join

ASJC Scopus subject areas

  • Applied Mathematics
  • Modelling and Simulation

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