Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Computational Fluid Dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive supercomputers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using Block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40%. This shows 46-170fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
Pages193-200
Number of pages8
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Field-Programmable Technology, ICFPT 2008 - Taipei, Taiwan, Province of China
Duration: 2008 Dec 72008 Dec 10

Other

Other2008 International Conference on Field-Programmable Technology, ICFPT 2008
CountryTaiwan, Province of China
CityTaipei
Period08/12/708/12/10

Fingerprint

Particle accelerators
Field programmable gate arrays (FPGA)
Computational fluid dynamics
Data storage equipment
Pipelines
Supercomputers
Subroutines
Random access storage
Data transfer
Software packages
Bandwidth
Engineers
Costs

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

Cite this

Morishita, H., Osana, Y., Fujita, N., & Amano, H. (2008). Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. In Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008 (pp. 193-200). [4762383] https://doi.org/10.1109/FPT.2008.4762383

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. / Morishita, Hirokazu; Osana, Yasunori; Fujita, Naoyuki; Amano, Hideharu.

Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. 2008. p. 193-200 4762383.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Morishita, H, Osana, Y, Fujita, N & Amano, H 2008, Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. in Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008., 4762383, pp. 193-200, 2008 International Conference on Field-Programmable Technology, ICFPT 2008, Taipei, Taiwan, Province of China, 08/12/7. https://doi.org/10.1109/FPT.2008.4762383
Morishita H, Osana Y, Fujita N, Amano H. Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. In Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. 2008. p. 193-200. 4762383 https://doi.org/10.1109/FPT.2008.4762383
Morishita, Hirokazu ; Osana, Yasunori ; Fujita, Naoyuki ; Amano, Hideharu. / Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. 2008. pp. 193-200
@inproceedings{ec13aaba61824e4baf64e995d7cf9b5b,
title = "Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs",
abstract = "Computational Fluid Dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive supercomputers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using Block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40{\%}. This shows 46-170fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.",
author = "Hirokazu Morishita and Yasunori Osana and Naoyuki Fujita and Hideharu Amano",
year = "2008",
doi = "10.1109/FPT.2008.4762383",
language = "English",
isbn = "9781424427963",
pages = "193--200",
booktitle = "Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008",

}

TY - GEN

T1 - Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

AU - Morishita, Hirokazu

AU - Osana, Yasunori

AU - Fujita, Naoyuki

AU - Amano, Hideharu

PY - 2008

Y1 - 2008

N2 - Computational Fluid Dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive supercomputers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using Block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40%. This shows 46-170fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.

AB - Computational Fluid Dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive supercomputers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using Block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40%. This shows 46-170fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.

UR - http://www.scopus.com/inward/record.url?scp=63049107218&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=63049107218&partnerID=8YFLogxK

U2 - 10.1109/FPT.2008.4762383

DO - 10.1109/FPT.2008.4762383

M3 - Conference contribution

AN - SCOPUS:63049107218

SN - 9781424427963

SP - 193

EP - 200

BT - Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008

ER -