Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

Toru Katagiri; Kazuei Hironaka; Hideharu Amano

doi:10.1109/NBiS.2012.87

Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

Toru Katagiri, Kazuei Hironaka, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3-DP needs to generate read/write addresses for accessing data memories, and counts a number of loops on PEs. Hence, PEs of MuCCRA-3-DP can not be used effectively for actual processing of applications. To solve this problem and improve performance. We extend the memory controller of MuCCRA-3-DP and named it MuCCRA-3-EXMC. PEs of MuCCRA-3-EXMC can be concentrated on executing the actual processing by the extended memory controller performing address generation and loop count. Evaluation results showed that MuCCRA-3-EXMC can improve its performance by 12-23% and reduce its energy consumption by 9-20% without a large increase of its area.

Original language	English
Title of host publication	Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012
Pages	826-831
Number of pages	6
DOIs	https://doi.org/10.1109/NBiS.2012.87
Publication status	Published - 2012 Dec 14
Event	2012 15th International Conference on Network-Based Information Systems, NBIS 2012 - Melbourne, VIC, Australia Duration: 2012 Sept 26 → 2012 Sept 28

Publication series

Name	Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012

Other

Other	2012 15th International Conference on Network-Based Information Systems, NBIS 2012
Country/Territory	Australia
City	Melbourne, VIC
Period	12/9/26 → 12/9/28

Keywords

MuCCRA-3
dynamic reconfiguration
energy consumption
flexible off-loading engine
memory controller

ASJC Scopus subject areas

Computer Networks and Communications
Information Systems

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/NBiS.2012.87

Cite this

Katagiri, T., Hironaka, K., & Amano, H. (2012). Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array. In Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012 (pp. 826-831). [6354932] (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012). https://doi.org/10.1109/NBiS.2012.87

Extension of memory controller equipped with MuCCRA-3-DP : Dynamically reconfigurable processor array. / Katagiri, Toru; Hironaka, Kazuei; Amano, Hideharu.

Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. 2012. p. 826-831 6354932 (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Katagiri, T, Hironaka, K & Amano, H 2012, Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array. in Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012., 6354932, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012, pp. 826-831, 2012 15th International Conference on Network-Based Information Systems, NBIS 2012, Melbourne, VIC, Australia, 12/9/26. https://doi.org/10.1109/NBiS.2012.87

Katagiri T, Hironaka K, Amano H. Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array. In Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. 2012. p. 826-831. 6354932. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012). doi: 10.1109/NBiS.2012.87

Katagiri, Toru ; Hironaka, Kazuei ; Amano, Hideharu. / Extension of memory controller equipped with MuCCRA-3-DP : Dynamically reconfigurable processor array. Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. 2012. pp. 826-831 (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

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abstract = "In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3-DP needs to generate read/write addresses for accessing data memories, and counts a number of loops on PEs. Hence, PEs of MuCCRA-3-DP can not be used effectively for actual processing of applications. To solve this problem and improve performance. We extend the memory controller of MuCCRA-3-DP and named it MuCCRA-3-EXMC. PEs of MuCCRA-3-EXMC can be concentrated on executing the actual processing by the extended memory controller performing address generation and loop count. Evaluation results showed that MuCCRA-3-EXMC can improve its performance by 12-23% and reduce its energy consumption by 9-20% without a large increase of its area.",

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AB - In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use PEs effectively. However, a prototype DRPA, MuCCRA-3-DP needs to generate read/write addresses for accessing data memories, and counts a number of loops on PEs. Hence, PEs of MuCCRA-3-DP can not be used effectively for actual processing of applications. To solve this problem and improve performance. We extend the memory controller of MuCCRA-3-DP and named it MuCCRA-3-EXMC. PEs of MuCCRA-3-EXMC can be concentrated on executing the actual processing by the extended memory controller performing address generation and loop count. Evaluation results showed that MuCCRA-3-EXMC can improve its performance by 12-23% and reduce its energy consumption by 9-20% without a large increase of its area.

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Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

UN SDGs

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