Fabrication and characterization of Si/SiGe quantum dots with capping gate

Tetsuo Kodera; Yuji Fukuoka; Kenta Takeda; Toshiaki Obata; Katsuharu Yoshida; Kentaro Sawano; Ken Uchida; Yasuhiro Shiraki; Seigo Tarucha; Shunri Oda

doi:10.1109/SNW.2012.6243291

Fabrication and characterization of Si/SiGe quantum dots with capping gate

Tetsuo Kodera, Yuji Fukuoka, Kenta Takeda, Toshiaki Obata, Katsuharu Yoshida, Kentaro Sawano, Ken Uchida, Yasuhiro Shiraki, Seigo Tarucha, Shunri Oda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.

Original language	English
Title of host publication	2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
DOIs	https://doi.org/10.1109/SNW.2012.6243291
Publication status	Published - 2012
Externally published	Yes
Event	2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012 - Honolulu, HI, United States Duration: 2012 Jun 10 → 2012 Jun 11

Publication series

Name	2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012

Other

Other	2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012
Country/Territory	United States
City	Honolulu, HI
Period	12/6/10 → 12/6/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SNW.2012.6243291

Cite this

Kodera, T, Fukuoka, Y, Takeda, K, Obata, T, Yoshida, K, Sawano, K, Uchida, K, Shiraki, Y, Tarucha, S & Oda, S 2012, Fabrication and characterization of Si/SiGe quantum dots with capping gate. in 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012., 6243291, 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012, 2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012, Honolulu, HI, United States, 12/6/10. https://doi.org/10.1109/SNW.2012.6243291

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title = "Fabrication and characterization of Si/SiGe quantum dots with capping gate",

abstract = "We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.",

author = "Tetsuo Kodera and Yuji Fukuoka and Kenta Takeda and Toshiaki Obata and Katsuharu Yoshida and Kentaro Sawano and Ken Uchida and Yasuhiro Shiraki and Seigo Tarucha and Shunri Oda",

year = "2012",

doi = "10.1109/SNW.2012.6243291",

language = "English",

isbn = "9781467309943",

series = "2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012",

booktitle = "2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012",

note = "2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012 ; Conference date: 10-06-2012 Through 11-06-2012",

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TY - GEN

T1 - Fabrication and characterization of Si/SiGe quantum dots with capping gate

AU - Kodera, Tetsuo

AU - Fukuoka, Yuji

AU - Takeda, Kenta

AU - Obata, Toshiaki

AU - Yoshida, Katsuharu

AU - Sawano, Kentaro

AU - Uchida, Ken

AU - Shiraki, Yasuhiro

AU - Tarucha, Seigo

AU - Oda, Shunri

PY - 2012

Y1 - 2012

N2 - We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.

AB - We study transport properties of quantum point contacts (QPCs) and quantum dots (QDs) with a global capping gate, fabricated on a Si/SiGe high electron mobility transistor (HEMT) wafer. By biasing the capping gate negatively, we succeed in making QPC operation point of surface Schottky gate negatively smaller and then reducing noise. We also observe Coulomb oscillations using a QD structure by suppressing charging noise with negative capping gate voltage.

UR - http://www.scopus.com/inward/record.url?scp=84867211370&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84867211370&partnerID=8YFLogxK

U2 - 10.1109/SNW.2012.6243291

DO - 10.1109/SNW.2012.6243291

M3 - Conference contribution

AN - SCOPUS:84867211370

SN - 9781467309943

T3 - 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012

BT - 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012

T2 - 2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012

Y2 - 10 June 2012 through 11 June 2012

ER -

Fabrication and characterization of Si/SiGe quantum dots with capping gate

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