Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

Toshikazu Mukaiyama, Ken Ichi Saito, Hiroki Ishikuro, Makoto Takamiya, Takuya Saraya, Toshiro Hiramoto

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

Original languageEnglish
Pages (from-to)1623-1626
Number of pages4
JournalSolid-State Electronics
Volume42
Issue number7-8
Publication statusPublished - 1998 Jul
Externally publishedYes

Fingerprint

Anisotropic etching
Silicon
Lithography
field effect transistors
etching
Wire
Fabrication
fabrication
silicon
SOI (semiconductors)
immunity
high current
lithography
simulation
wire

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

Cite this

Mukaiyama, T., Saito, K. I., Ishikuro, H., Takamiya, M., Saraya, T., & Hiramoto, T. (1998). Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique. Solid-State Electronics, 42(7-8), 1623-1626.

Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique. / Mukaiyama, Toshikazu; Saito, Ken Ichi; Ishikuro, Hiroki; Takamiya, Makoto; Saraya, Takuya; Hiramoto, Toshiro.

In: Solid-State Electronics, Vol. 42, No. 7-8, 07.1998, p. 1623-1626.

Research output: Contribution to journalArticle

Mukaiyama, T, Saito, KI, Ishikuro, H, Takamiya, M, Saraya, T & Hiramoto, T 1998, 'Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique', Solid-State Electronics, vol. 42, no. 7-8, pp. 1623-1626.
Mukaiyama T, Saito KI, Ishikuro H, Takamiya M, Saraya T, Hiramoto T. Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique. Solid-State Electronics. 1998 Jul;42(7-8):1623-1626.
Mukaiyama, Toshikazu ; Saito, Ken Ichi ; Ishikuro, Hiroki ; Takamiya, Makoto ; Saraya, Takuya ; Hiramoto, Toshiro. / Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique. In: Solid-State Electronics. 1998 ; Vol. 42, No. 7-8. pp. 1623-1626.
@article{a27a27a3ed264e728e7ac6c870527e98,
title = "Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique",
abstract = "A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.",
author = "Toshikazu Mukaiyama and Saito, {Ken Ichi} and Hiroki Ishikuro and Makoto Takamiya and Takuya Saraya and Toshiro Hiramoto",
year = "1998",
month = "7",
language = "English",
volume = "42",
pages = "1623--1626",
journal = "Solid-State Electronics",
issn = "0038-1101",
publisher = "Elsevier Limited",
number = "7-8",

}

TY - JOUR

T1 - Fabrication of gate-all-around MOSFET by silicon anisotropic etching technique

AU - Mukaiyama, Toshikazu

AU - Saito, Ken Ichi

AU - Ishikuro, Hiroki

AU - Takamiya, Makoto

AU - Saraya, Takuya

AU - Hiramoto, Toshiro

PY - 1998/7

Y1 - 1998/7

N2 - A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

AB - A novel fabrication process of gate-all-around (GAA) MOSFETs using an anisotropic etching technique has been proposed. In this technology, the channel width of the GAA device is not limited by the lithography resolution and the density of the wire channel is doubled. The two-dimensional device simulation shows much better short channel immunity of GAA devices than that of single gate and double gate SOI MOSFETs. The simulation also shows that the new GAA devices we have proposed have higher current drivability than the conventional GAA and single gate SOI devices.

UR - http://www.scopus.com/inward/record.url?scp=0032121382&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032121382&partnerID=8YFLogxK

M3 - Article

VL - 42

SP - 1623

EP - 1626

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 7-8

ER -