Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2

Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%. copyright

Original languageEnglish
Title of host publication2008 14th Asia-Pacific Conference on Communications, APCC 2008
Publication statusPublished - 2008 Dec 1
Event2008 14th Asia-Pacific Conference on Communications, APCC 2008 - Akihabara, Tokyo, United States
Duration: 2008 Oct 142008 Oct 16

Publication series

Name2008 14th Asia-Pacific Conference on Communications, APCC 2008

Other

Other2008 14th Asia-Pacific Conference on Communications, APCC 2008
CountryUnited States
CityAkihabara, Tokyo
Period08/10/1408/10/16

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Communication

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    Kihara, T., Shimizu, S., Arakawa, Y., Yamanaka, N., & Shiba, K. (2008). Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2. In 2008 14th Asia-Pacific Conference on Communications, APCC 2008 [4773784] (2008 14th Asia-Pacific Conference on Communications, APCC 2008).